Stacked CMOS Transistor Isolation via Oxidized Source/Drain Surfaces
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Solution Overview
Problem
As the distance between gates of transistors in stacked arrangements decreases, it becomes difficult to electrically isolate upper and lower transistors, particularly in complementary metal-oxide-semiconductor (CMOS) configurations, making it challenging to fabricate stacked transistors with a high aspect ratio (A/R) and control source/drain leakage current.
Innovation Solution
The method involves forming isolation patterns through oxidation processes on the sidewalls of channel patterns and outermost surfaces of source/drain regions, along with leakage protection regions, to create electrical isolation between stacked transistors, using techniques like plasma or thermal oxidation and epitaxial growth to form insulating layers and patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the distance between gates of transistors in stacked arrangements is reduced to increase density, then the density of the integrated circuit device is improved, but the ability to electrically isolate upper and lower transistors deteriorates
Solution Approach 1:
The patent divides the isolation structure into multiple segments: first isolation patterns formed by oxidizing surfaces of source/drain regions, second isolation patterns formed between first source/drain regions, and leakage protection regions. This segmented approach enables effective electrical isolation even when gate pitch is reduced, resolving the contradiction between increased density and maintained isolation reliability.
Solution Approach 2:
The patent introduces intermediary insulating structures including first isolation patterns (oxidized surfaces), second isolation patterns (dielectric layers), and leakage protection regions. These intermediary elements act as mediators between the upper and lower transistors, providing electrical isolation while allowing the transistors to be positioned closer together for increased density.
2Reliability
If stacked transistors are formed with high aspect ratio to improve performance, then the performance of the integrated circuit device is improved, but the difficulty of fabricating CMOS transistors in stacked arrangement increases
Solution Approach 1:
The patent performs preliminary actions by forming leakage protection regions and first isolation patterns before forming the source/drain regions. This preliminary isolation structure is established to prevent leakage current paths during subsequent fabrication steps, enabling high aspect ratio stacked transistors to be manufactured without compromising electrical isolation or device performance.
Solution Approach 2:
The patent applies different isolation strategies to different locations: first isolation patterns on the surfaces of source/drain regions, second isolation patterns between adjacent source/drain regions, and leakage protection regions in specific areas. This localized quality approach addresses fabrication challenges at each specific location, enabling successful manufacture of high aspect ratio stacked CMOS transistors.
3Reliability
If oxidation process is performed to form isolation patterns, then electrical isolation between stacked transistors is improved, but the complexity of the fabrication process increases
Solution Approach 1:
The patent merges multiple functions into the oxidation process: forming first isolation patterns on source/drain surfaces, creating leakage protection regions, and establishing initial electrical isolation all in a single oxidation step. This consolidation improves electrical isolation while minimizing the increase in fabrication process complexity by combining multiple beneficial effects into one process step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the fabrication of stacked transistors with high A/R and reduced contact poly pitch (CPP), effectively isolating upper and lower devices and preventing electrical contact, while maintaining device performance.
Implementation Method 1
performing an oxidation process to oxidize portions of upper and lower surfaces of the second source/drain regions and opposing side surfaces of the first channel pattern to form first isolation patterns
Implementation Method 2
epitaxially growing the second source/drain regions of the second transistor on the opposing side surfaces of the second channel pattern
Implementation Method 3
epitaxially growing the first source/drain regions of the first transistor at the opposing ends of the first channel pattern
Data Source
AI summary
A method of forming an integrated circuit device includes providing a stacked transistor structure on a substrate. The stacked transistor structure includes a first channel pattern of a first transistor and a second channel pattern of a second transistor stacked on the first channel pattern. Second source/drain regions of the second transistor are formed at opposing ends of the second channel pattern, and an oxidation process is performed to oxidize upper and lower surfaces of the second source/drain regions and side surfaces of the first channel. First source/drain regions of the first transistor are then formed at opposing ends of the first channel pattern. Related devices and fabrication methods are also discussed.