Stacked CMOS Channel Layout for Lattice-Mismatch Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Lattice mismatch between III-V and IV semiconductor epitaxial layers and silicon substrates leads to crystal defects, such as threading dislocations and twins, which propagate into device layers, causing performance issues in electronic and optoelectronic devices, and existing techniques like Aspect Ratio Trapping and thick buffer deposition are time-consuming, expensive, and difficult to scale with smaller device sizes.
Innovation Solution
A process for heterogeneous channel device fabrication that allows simultaneous fabrication of P-type and N-type metal-oxide-semiconductor (MOS) devices using a single lithography and patterning step, enabling selective access to buried and transferred layers, thereby reducing the need for additional interconnect layers and minimizing mask counts, and allowing for direct formation of gates on both channel types without additional lithography steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Aspect Ratio Trapping or thick buffer deposition is used to manage lattice mismatch defects, then defect density in device layers is reduced, but fabrication time and process complexity increase significantly
Solution Approach 1:
The patent applies preliminary action by forming a patterned mask layer before depositing the channel layer, which pre-defines the regions where defects will be trapped or excluded. This preliminary patterning allows subsequent single-step deposition to simultaneously create both P-type and N-type devices with proper defect management, eliminating the need for time-consuming sequential processing steps.
Solution Approach 2:
The patent segments the device structure into distinct P-type and N-type regions defined by the patterned mask layer. This segmentation allows different channel types to be formed in separate regions simultaneously, with each region's defect management optimized independently through the patterning design, rather than requiring separate fabrication processes.
2Manufacturing precision
If separate lithography and patterning steps are used for P-type and N-type devices, then device performance is optimized, but manufacturing complexity and cost increase
Solution Approach 1:
The patent merges the fabrication processes for P-type and N-type devices into a single lithography and patterning step. The patterned mask layer is designed to simultaneously define both device types, allowing both to be formed in one deposition process. This merging maintains manufacturing precision by using carefully designed patterns while dramatically reducing process complexity.
Solution Approach 2:
The patterned mask layer serves multiple functions: it defines P-type device regions, defines N-type device regions, and acts as a template for simultaneous deposition of both channel types. This multi-functionality eliminates the need for separate lithography steps for each device type, reducing overall fabrication complexity while maintaining precision.
3Adaptability or versatility
If additional interconnect layers are added to access buried and transferred layers, then device functionality is enhanced, but device scaling to smaller sizes becomes difficult
Solution Approach 1:
The patent transitions from planar interconnect architecture to vertical stacking by forming P-type and N-type channels in vertically stacked layers. The patterned mask layer enables direct formation of gates on both channel types within the same lateral footprint, accessing buried and transferred layers through vertical integration rather than additional lateral interconnect layers, thus enabling scaling to smaller device sizes.
Data Source
Figure 1~3
Figure 4~6
Figure 7~9
AI summary
An embodiment includes an apparatus comprising: an N layer comprising an NMOS device having a N channel, source, and drain that are all intersected by a first horizontal axis that is parallel to a substrate; a P layer comprising a PMOS device having a P channel, source, and drain that are all intersected by a second horizontal axis that is parallel to the substrate; a first gate, corresponding to the N channel, which intersects the second horizontal axis; and a second gate, corresponding to the P channel, which intersects the first horizontal axis. Other embodiments are described herein.