Stacked CMOS Pixel Sensor Layout for Gate Dielectric Scaling
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Solution Overview
Problem
Scaling down transistors in CMOS image sensors is challenging due to varying gate dielectric thicknesses, which complicates fabrication and degrades sensor performance, making it difficult to achieve lower costs, higher integration density, and better performance.
Innovation Solution
A stacked CMOS image sensor design where the pixel sensor spans multiple IC chips, with a single gate dielectric thickness at one IC chip and reduced or varying thicknesses at another, allowing for scaling down the pixel sensor without reducing the photodetector size, thereby maintaining performance and enabling additional functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If transistors are scaled down in CMOS image sensors, then integration density and manufacturing cost are improved, but fabrication complexity increases due to varying gate dielectric thicknesses and performance degrades
Solution Approach 1:
The pixel sensor is divided into two separate IC chips: the first IC chip contains the photodetector and first transistor with first gate dielectric thickness, while the second IC chip contains the second transistor with second gate dielectric thickness. This segmentation allows each chip to be optimized independently for its specific transistor gate dielectric requirements, avoiding the fabrication complexity that would arise from integrating transistors with different gate dielectric thicknesses on a single chip.
2Volume of moving object
If transistors are scaled down in CMOS image sensors, then device size is reduced, but fabrication complexity increases due to varying gate dielectric thicknesses
Solution Approach 1:
The pixel sensor is divided into two separate IC chips: the first IC chip contains the photodetector and first transistor with first gate dielectric thickness, while the second IC chip contains the second transistor with second gate dielectric thickness. This segmentation allows each chip to be optimized independently for its specific transistor gate dielectric requirements, avoiding the fabrication complexity that would arise from integrating transistors with different gate dielectric thicknesses on a single chip.
Solution Approach 2:
The invention transitions from a planar integration approach to a three-dimensional stacked architecture. By stacking the first IC chip (containing photodetector and first transistor) with the second IC chip (containing second transistor), the system achieves vertical integration that reduces the overall device footprint while maintaining the ability to use different gate dielectric thicknesses on separate chips, thereby reducing fabrication complexity.
3Manufacturing precision
If photodetector size is reduced to scale down pixel sensor, then integration density is improved, but performance degrades
Solution Approach 1:
The invention transitions from a planar integration approach to a three-dimensional stacked architecture. By stacking the first IC chip (containing photodetector and first transistor) with the second IC chip (containing second transistor), the system achieves vertical integration that reduces the overall device footprint while maintaining the ability to use different gate dielectric thicknesses on separate chips, thereby reducing fabrication complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the scaling down of the pixel sensor without degrading its performance, even at small sizes, by distributing transistors across multiple chips, reducing complexity, and utilizing unused space for additional functionality.
Implementation Method 1
The photodetector is configured accumulate charge in response to incident radiation
Data Source
AI summary
Various embodiments of the present disclosure are directed towards a stacked complementary metal-oxide semiconductor (CMOS) image sensor in which a pixel sensor spans multiple integrated circuit (IC) chips and has only a first gate dielectric thickness at a first IC chip at which a photodetector of the of the pixel sensor is arranged. Further, the pixel sensor has only one or more second gate dielectric thicknesses at a second IC chip that is stacked with the first IC chip, and the one or more second gate dielectric thicknesses is/are less than or equal to the first gate dielectric thickness. The first and second gate dielectric thicknesses correspond to transistors of the pixel sensor, which form a pixel circuit of the pixel sensor configured to facilitate readout of the photodetector.