3D Stacked CMOS Image Sensor for Pixel Area Trade-Offs
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Solution Overview
Problem
The existing CMOS image sensors face limitations in performance due to the flat layout of photosensitive and reading circuit areas, which restricts the balance and expansion of working areas within a limited pixel area, thereby limiting device sensitivity and stability.
Innovation Solution
The method involves forming a CMOS image sensor with photosensitive doped layers and electrical devices in different layers, allowing for increased space utilization perpendicular to the substrate surface, thereby expanding the working areas of both the photosensitive and reading circuit areas without surface area constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the photosensitive area and reading circuit area are arranged in a plane, then the device structure is simple, but the working areas are limited within the pixel area
Solution Approach 1:
The patent transitions from a planar arrangement to a three-dimensional stacked structure, placing the photosensitive area and reading circuit area in different layers. This vertical stacking enables both areas to expand without increasing the pixel footprint, resolving the contradiction between structural simplicity and area limitation.
2Measurement precision
If the pixel density is increased, then the imaging resolution is improved, but the working areas of photosensitive and reading circuit areas are reduced
Solution Approach 1:
By stacking the photosensitive area and reading circuit area vertically, the patent enables higher pixel density while maintaining adequate working areas for both functions. The three-dimensional arrangement decouples the relationship between pixel density and working area that exists in planar designs.
3Reliability
If the working area of photosensitive area is increased, then the sensitivity is improved, but the area available for reading circuit area is reduced
Solution Approach 1:
The vertical stacking architecture allows the photosensitive area to be enlarged in the vertical dimension without encroaching on the reading circuit area, which resides in a different layer. This resolves the area trade-off between sensitivity improvement and reading circuit capacity.
4Reliability
If the working area of reading circuit area is increased, then the device stability is improved, but the area available for photosensitive area is reduced
Solution Approach 1:
By placing the reading circuit area in a separate layer above the photosensitive area, the patent enables enlargement of the reading circuit working area without reducing the photosensitive area. The vertical separation eliminates the area competition that exists in planar configurations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the sensitivity of the photosensitive doped layers for optical signal reception, improves the stability of the CMOS image sensor by accommodating more complex electrical devices, and reduces noise, ultimately leading to improved overall device performance.
Implementation Method 1
A PN junction in the photosensitive area is used to receive an optical signal
Data Source
AI summary
The present disclosure provides a CMOS image sensor and a method for forming the same. The method includes: forming a substrate, a plurality of photosensitive doped layers on the substrate, an isolation layer on the plurality of photosensitive doped layers, and an active layer on the isolation layer, wherein the substrate comprises a plurality of mutually discrete pixel areas, and each photosensitive doped layer is respectively disposed on each pixel area; forming an electrical device in the active layer and on the active layer; forming an interconnection structure in the isolation layer and the active layer, wherein the plurality of photosensitive doped layers are electrically coupled with the electrical device by the interconnection structure. The method can increase working areas of a photosensitive area and a reading circuit area simultaneously, thereby improving a device performance.