3D Stacked CMOS Image Sensor Structure for Lower Pixel Cross-Talk
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Solution Overview
Problem
As transistor devices shrink in size, there is a need for improved processing and performance of optical images in image sensors, particularly in complementary metal oxide semiconductor (CMOS) image sensors, to enhance their functionality and efficiency.
Innovation Solution
A 3D stacked CMOS image sensor structure is developed, incorporating a System-on-Chip (SOC) wafer, Application-Specific Integrated Circuit (ASIC) wafers, and metal-insulator-metal (MIM) capacitors, connected through through-silicon-via (TSV) structures, with thin film transistors for managing photodiode signals and reducing cross-talk between pixels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor devices are shrunk in size to increase processing capacity, then device integration and processing capability are improved, but signal management quality and cross-talk reduction become more difficult
Solution Approach 1:
The patent transitions from planar 2D transistor arrangement to 3D vertical stacking architecture. Multiple transistor layers are stacked vertically with interconnect structures connecting different layers, enabling increased processing capacity while maintaining signal integrity through controlled vertical pathways that reduce cross-talk between adjacent pixels.
Solution Approach 2:
The patent divides the image sensor into multiple discrete layers including photodetector layer, transfer gate layer, floating diffusion layer, and interconnect layers. Each layer is independently formed and optimized, allowing separate control of signal generation, transfer, and readout functions while reducing interference between components.
2Adaptability or versatility
If more processing elements are added to enhance image processing, then functionality is improved, but device complexity increases
Solution Approach 1:
The patent employs vertical stacking to add processing functionality in the third dimension rather than expanding horizontally. Multiple functional layers (photodetectors, transfer gates, floating diffusions, interconnects) are stacked vertically, enabling complex image processing capabilities while maintaining a compact footprint and systematic structure.
Solution Approach 2:
The patent designs multi-functional transistor structures that serve multiple purposes: photodetectors generate signals, transfer gates move signals, floating diffusions amplify and store signals, and interconnects route signals. Each structural element is optimized to perform multiple functions within the stacked architecture, reducing the need for separate dedicated components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances image processing capabilities and device performance by improving signal management and reducing cross-talk, thereby increasing the efficiency and effectiveness of image sensors.
Implementation Method 1
An image sensor typically includes an array of pixel sensors which absorb radiation and convert the sensed radiation into electrical signals
Data Source
AI summary
A semiconductor device is provided. The device comprises first semiconductor wafer comprising first BEOL structure disposed on first side of first substrate, the first BEOL structure comprising first metallization layer disposed over the first substrate, second metallization layer disposed over the first metallization layer, first storage device disposed between the first and second metallization layers, and first transistor contacting the first storage device, and a first bonding layer disposed over the first BEOL structure. The device also comprises second semiconductor wafer comprising second BEOL structure disposed on first side of second substrate, the second BEOL structure comprising third metallization layer disposed over the second substrate, fourth metallization layer disposed over the third metallization layer, second storage device disposed between the third and fourth metallization layers, and second transistor contacting the second storage device, and second bonding layer disposed over the second BEOL structure and contacting the first bonding layer.