Stacked CMOS Image Sensor Layout for High Pixel Density
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Solution Overview
Problem
Existing CMOS image sensors face challenges in increasing pixel density without reducing photodiode area, leading to issues like full well capacitance, lag, and white pixel problems, which limit further reduction in pixel size.
Innovation Solution
A CMOS image sensor is manufactured using a pixel cell circuit with a photodiode on a bottom semiconductor substrate and a CMOS pixel readout circuit on a top semiconductor substrate, connected via an electrotransfer structure through a dielectric buried layer, allowing for a larger photodiode size without increasing pixel cell circuit size, and incorporating a vertical gate transmission transistor to reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If photodiode area is reduced to increase pixel density, then pixel density increases, but full well capacitance decreases and lag/white pixel problems occur
Solution Approach 1:
The patent transitions from a planar 2D layout to a 3D stacked architecture by separating the photodiode and readout circuit onto different semiconductor substrates (bottom and top substrates respectively). This vertical dimensionality change allows the photodiode area to be maximized for high full well capacitance while the readout circuit occupies the upper layer, achieving high pixel density without sacrificing photodiode size.
Solution Approach 2:
The image sensor is segmented into functionally independent layers: the bottom semiconductor substrate contains the photodiode array optimized for light sensing, while the top semiconductor substrate contains the CMOS pixel readout circuit. This segmentation allows each layer to be independently optimized - large photodiode area for high capacitance and proper signal processing for the readout circuit.
2Productivity
If photodiode area is reduced to increase pixel density, then pixel density increases, but lag and white pixel problems worsen
Solution Approach 1:
By moving the readout circuit to the top substrate and keeping the photodiode on the bottom substrate, the patent maintains large photodiode area which directly improves full well capacitance and eliminates lag/white pixel issues while achieving high density through vertical stacking.
3Productivity
If pixel size is reduced to increase density, then pixel density increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent resolves the manufacturing precision challenge by moving the alignment burden to the wafer-level bonding process rather than requiring sub-micron feature fabrication. The photodiode and readout circuit are formed on separate wafers with standard precision, then bonded together, avoiding the need for ultra-precise miniaturization of individual pixel components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-density, small-pixel size CMOS image sensors with increased full well capacitance, improved lag and white pixel issues, and reduced power consumption, while maintaining or enhancing photodiode size and fill factor.
Implementation Method 1
The photodiode D1, when irradiated by light, generates photo-induced electrons
Data Source
AI summary
The present application discloses a CMOS image sensor. A pixel cell circuit comprises a photodiode and a CMOS pixel readout circuit. The pixel cell circuit is formed on an SOI substrate, and the photodiode is formed on a bottom semiconductor substrate. The CMOS pixel readout circuit is formed on a top semiconductor substrate. A photo-induced carrier of the photodiode is connected to the CMOS pixel readout circuit by means of an electrotransfer structure passing through a dielectric buried layer. The present application also discloses a method for manufacturing a CMOS image sensor. The present application can increase a pixel cell density without reducing a photodiode area, thus achieving an ultra-high CMOS image sensor density and improving the device quality.