Stacked CMOS Image Sensor Dynamic Range Architecture
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Solution Overview
Problem
Conventional CMOS image sensors struggle to achieve high dynamic range due to full well limitation and noise floor, limiting their application in capturing a wide range of illumination conditions from night vision to bright sunlight, and require more silicon area for increased frame rates, which hinders miniaturization.
Innovation Solution
A stacked CMOS image sensor design with pixel sub-arrays on a first semiconductor die and shared readout circuitry on a second die, allowing pixel cells to share a single readout circuit, enabling high-speed and low-power parallel readout and increasing dynamic range without increasing silicon area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If one column of pixels shares one readout circuit to increase frame rate, then frame rate is improved, but silicon area increases
Solution Approach 1:
The patent transitions from a planar architecture to a three-dimensional stacked architecture, placing pixel cells on one die and readout circuits on another die connected via through-silicon vias. This vertical stacking enables multiple pixel columns to share fewer readout circuits without increasing the lateral silicon area, thereby increasing frame rate while maintaining compact form factor.
Solution Approach 2:
The patent divides the image sensor into separate functional modules: pixel cell arrays on one die and readout circuitry on another die. This segmentation allows independent optimization of each module and enables parallel readout operations across multiple pixel columns, improving frame rate without proportionally increasing total silicon area.
2Ease of manufacture
If conventional CCD and CMOS sensors are used, then manufacturing is simple, but dynamic range is limited to 60-70 dB
Solution Approach 1:
The stacked architecture separates photodetection and readout functions onto different dies, enabling advanced HDR processing techniques such as dual gain amplification and multiple exposure capture without complicating the basic CMOS manufacturing process. This vertical integration achieves 100 dB dynamic range while maintaining compatibility with standard semiconductor fabrication.
Solution Approach 2:
The patent employs dual gain readout circuits that can switch between high gain and low gain modes, and implements variable exposure times for different pixel regions. These parameter changes enable the sensor to capture both dim and bright scenes simultaneously, achieving 100 dB dynamic range while using conventional CMOS technology.
Data Source
AI summary
Method of implementing stacked chip HDR algorithm in image sensor starts with pixel array capturing first frame with first exposure time and second frame with a second exposure time that is longer or shorter than the first exposure time. Pixel array is disposed in first semiconductor die and is partitioned into pixel sub-arrays. Each pixel sub-array is arranged into pixel groups, and each pixel group is arranged into pixel cell array. Readout circuits disposed in second semiconductor die acquire image data of first and second frame. Each pixel sub-array is coupled to a corresponding readout circuit through a corresponding one of a plurality of conductors. ADC circuits convert image data from first and second frames to first and second ADC outputs. Function logic on the second semiconductor die adding first and second ADC outputs to generate a final ADC output. Other embodiments are also described.