3D Stacked CMOS Image Sensor for Noise and Crosstalk Isolation
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Solution Overview
Problem
The scaling down of CMOS image sensor pixels increases transistor noise and reduces chip space for deep trench isolation (DTI) structures, leading to increased light and electrical crosstalk between pixels and transistors, which degrades device performance.
Innovation Solution
A three-chip CMOS image sensor design where pixels, transfer transistors, and diffusion wells are formed on a first chip, source followers, reset transistors, and row select transistors are formed on a second chip, and application-specific circuits are on a third chip, with interconnect structures and DTI structures to reduce noise and crosstalk.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If CMOS image sensors are scaled down to reduce device size, then miniaturization is achieved, but transistor noise increases and light/electrical crosstalk worsens due to reduced chip space for deep trench isolation structures
Solution Approach 1:
The patent divides the image sensor into three separate chips: first chip containing pixels and transfer transistors, second chip containing source followers and reset transistors, and third chip containing application-specific circuits. This segmentation allows each chip to be optimized independently, with sufficient space for deep trench isolation structures on each chip, thereby reducing crosstalk and transistor noise while maintaining overall device miniaturization
Solution Approach 2:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked architecture by bonding multiple chips vertically. This dimensional change enables increased transistor sizes and wider deep trench isolation structures on each individual chip while keeping the overall device footprint small, effectively resolving the contradiction between miniaturization and noise/crosstalk reduction
2Volume of moving object
If chip space is reduced for miniaturization, then device size decreases, but space for deep trench isolation structures is reduced, increasing light and electrical crosstalk
Solution Approach 1:
By segmenting the image sensor into three separate chips, each chip can be designed with adequate space for deep trench isolation structures between pixels and transistor regions. This eliminates the crosstalk problem that would occur in a miniaturized single-chip design, as each chip maintains sufficient isolation space despite the overall device being compact due to vertical stacking
Solution Approach 2:
The patent introduces deep trench isolation structures as intermediary elements between adjacent pixels and transistor regions on each chip. These DTI structures act as physical barriers that block both light and electrical signals, preventing crosstalk between neighboring elements while allowing the chip to maintain a compact form factor
3Productivity
If transistor size is reduced for miniaturization, then device density increases, but transistor noise increases
Solution Approach 1:
The patent segments the transistor functions across three different chips: transfer transistors on the first chip, source followers and reset transistors on the second chip, and application-specific circuits on the third chip. This segmentation allows each transistor to be sized optimally for its function without the constraints of miniaturization, reducing transistor noise while maintaining high device density through vertical stacking
Solution Approach 2:
By moving to a three-dimensional stacked architecture, the patent increases device density not by reducing transistor size in the planar dimension, but by adding the vertical dimension. This allows transistors to maintain larger sizes with lower noise while achieving high density through chip stacking, effectively resolving the contradiction between density and noise
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The three-chip design increases transistor sizes, reduces noise, and provides more space for wider DTI structures, thereby decreasing light and electrical crosstalk, enhancing device performance by improving isolation between pixels.
Implementation Method 1
Semiconductor image sensors are used to sense radiation, such as light, and convert the sensed radiation into electrical signals. These devices utilize an array of pixels, such as photodiodes, to sense radiation that is projected toward the pixels.
Data Source
AI summary
The present disclosure describes a three-chip complementary metal-oxide-semiconductor (CMOS) image sensor and a method for forming the image sensor. The image sensor a first chip including a plurality of image sensing elements, transfer transistors and diffusion wells corresponding to the plurality of image sensing elements, a ground node shared by the plurality of image sensing elements, and deep trench isolation (DTI) structures extending from the shared ground node and between adjacent image sensing elements of the plurality of image sensing elements. The image sensor further includes a second chip bonded to the first chip and including a source follower, a reset transistor, a row select transistor, and an in-pixel circuit, where the source follower is electrically coupled to the diffusion wells. The image sensor further includes a third chip bonded to the second chip and including an application-specific circuit, where the application-specific circuit is electrically coupled to the in-pixel circuit.