Stacked CMOS Image Sensor Layout for Pixel Shrink and Light Blocking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Stacked back-illuminated CMOS image sensors face challenges in miniaturizing pixels while maintaining effective light-blocking measures, which degrades parasitic light sensitivity characteristics and reduces saturation charge quantity.
Innovation Solution
A solid-state imaging device is developed with a first semiconductor substrate for photoelectric conversion and a second semiconductor substrate for charge retention, where a through electrode penetrates the second substrate to transfer charges, allowing for miniaturization while maintaining effective light-blocking and parasitic light sensitivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If light-blocking measures are taken to improve parasitic light sensitivity characteristics, then parasitic light sensitivity is improved, but the area of photodiodes becomes small and saturation charge quantity is sacrificed
Solution Approach 1:
The patent transitions from a planar arrangement to a three-dimensional stacked architecture, separating photodiodes and memory into different semiconductor substrates stacked in the vertical dimension. This spatial reconfiguration allows sufficient light-blocking measures in the horizontal plane without compromising photodiode area, as the memory is now located in a different spatial layer.
Solution Approach 2:
The imaging device is divided into multiple independent semiconductor substrates: a first substrate containing photodiodes and a second substrate containing memory. This segmentation allows each component to be optimized independently for its specific function, enabling effective light-blocking for the photodiodes without interfering with the memory structure.
2Area of moving object
If miniaturization of pixels is implemented, then pixel density is improved, but maintaining effective light-blocking measures becomes difficult and parasitic light sensitivity characteristics degrade
Solution Approach 1:
By moving memory to a stacked substrate in the vertical dimension, the patent frees up horizontal space in the photodiode layer, enabling pixel miniaturization without compromising light-blocking effectiveness. The separated architecture maintains adequate light-blocking measures even as pixel dimensions are reduced.
3Device complexity
If memory is disposed in the same silicon layer as photodiodes, then device complexity is reduced, but parasitic light sensitivity characteristics are degraded
Solution Approach 1:
The patent segments the device into multiple semiconductor substrates, placing photodiodes in a first substrate and memory in a second substrate. This physical separation eliminates parasitic light sensitivity issues that would arise from co-locating these components in the same layer, while the modular stacked design keeps the overall device complexity manageable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables the miniaturization of pixels while enhancing parasitic light sensitivity characteristics and saturation charge quantity, effectively addressing the limitations of existing technologies.
Implementation Method 1
a through electrode that penetrates the second semiconductor substrate, and transmits the electric charge transferred from the transfer transistor or the voltage to the charge/voltage retention portion
Implementation Method 2
a photoelectric conversion portion that photoelectrically converts incident light
Data Source
AI summary
The present technology relates to a solid-state imaging device compatible with miniaturization of pixels, a method for manufacturing the solid-state imaging device, and an electronic apparatus. The solid-state imaging device is formed by joining a front surface side as the wiring layer formation surface of the first semiconductor substrate to a back surface side of the second semiconductor substrate. The first semiconductor substrate includes a photodiode and a transfer transistor. The second semiconductor substrate includes a charge/voltage retention portion that retains the electric charge transferred by the transfer transistor or the voltage corresponding to the electric charge. The solid-state imaging device includes a through electrode that penetrates the second semiconductor substrate, and transmits the electric charge or the voltage to the charge/voltage retention portion. The present technology can be applied to solid-state imaging devices and the like, for example.