Stacked CMOS Structure for Higher Transistor Density
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Solution Overview
Problem
As technology advances, dimension shrinkage becomes increasingly challenging for increasing transistor density in semiconductor devices due to physical and material limitations, necessitating novel configurations to enhance transistor density beyond traditional CMOS devices with side-by-side NMOS and PMOS transistors.
Innovation Solution
The implementation of a stacked device structure where NMOS and PMOS transistors are vertically stacked to form CMOS devices, using semiconductor-on-insulator substrates for n-type GAA transistors and bulk Si for p-type GAA or FinFET processes, allowing for higher transistor density through separate fabrication and bonding of nMOS and pMOS transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If dimension shrink is used to increase transistor density, then transistor density increases, but physical and material limitations make it increasingly challenging
Solution Approach 1:
The patent transitions from two-dimensional planar transistor arrangements to three-dimensional vertically stacked configurations. Multiple transistor layers are stacked along the vertical axis, enabling increased transistor density without further lateral dimension shrinkage. This dimensional transition allows continued scaling while avoiding the physical and material limitations encountered in traditional planar architectures.
2Quantity of substance
If traditional side-by-side NMOS and PMOS configuration is used, then CMOS device functionality is achieved, but transistor density is lower compared to stacked configurations
Solution Approach 1:
The patent implements vertically stacked NMOS and PMOS transistor layers along the vertical axis, replacing the traditional horizontal side-by-side arrangement. This three-dimensional stacking enables higher transistor density while maintaining CMOS functionality through separate n-type and p-type transistor layers that can be independently fabricated and then bonded together.
3Quantity of substance
If separate fabrication of nMOS and pMOS transistors is performed, then higher transistor density is achieved through stacking, but fabrication process complexity increases
Solution Approach 1:
The patent divides the CMOS device fabrication into separate segments: nMOS transistor fabrication on one substrate and pMOS transistor fabrication on another substrate. These segmented fabrication processes can be optimized independently, and the separately fabricated transistor layers are subsequently bonded together to form the final stacked CMOS device, enabling higher density while managing process complexity through modular fabrication.
Solution Approach 2:
The patent introduces carrier substrates as intermediary elements during the fabrication process. nMOS and pMOS transistors are first fabricated on separate carrier substrates, which then serve as intermediaries for subsequent bonding operations. This intermediary approach simplifies the integration of separately fabricated transistor layers into the final stacked configuration.
Data Source
AI summary
A complementary metal oxide semiconductor (CMOS) device includes a transistor of a first type formed over a first substrate, and a transistor of a second type formed over a second substrate. The CMOS device is formed when the transistor of the first type formed on the first substrate is bonded to the transistor of the second type formed over the second substrate.