Stacked CMOS Pixel Layout Without STI for Sub-0.7 µm Scaling
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Solution Overview
Problem
Transistors in CMOS image sensors limit scaling down due to substrate etching during shallow trench isolation (STI) formation, causing crystalline damage and leakage/dark current, which reduces photodetector performance and limits the size of the photodetector, thereby hindering further scaling of the image sensor.
Innovation Solution
A stacked CMOS image sensor design that omits STI structures at the first IC chip, utilizing a shallow well, deep well, and deep trench isolation (DTI) structure for electrical isolation, allowing a larger photodetector and enabling enhanced scaling without significant performance tradeoffs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If STI structures are formed during manufacturing, then electrical isolation between transistors is achieved, but crystalline damage and leakage current increase, reducing photodetector performance
Solution Approach 1:
The patent removes the STI structure from the photodetector region entirely, extracting the harmful isolation method that causes crystalline damage. Instead, a simplified structure without STI is used at the photodetector, eliminating the source of damage while maintaining overall device functionality through alternative isolation approaches in other regions.
Solution Approach 2:
The patent applies different structural qualities to different regions: the photodetector region uses a simplified structure without STI to avoid damage, while other regions of the device may retain STI structures where they are beneficial. This localized differentiation allows optimization for photodetector performance without compromising overall device isolation requirements.
2Reliability
If photodetector size is increased to improve capacity, then charge transfer is enhanced, but device scaling is limited by transistor size constraints
Solution Approach 1:
The patent transitions from planar scaling to three-dimensional stacking, arranging photodetectors, transistors, and isolation structures in multiple vertical layers. This allows the photodetector to achieve larger effective area and improved capacity in the vertical dimension while maintaining small pixel pitch in the horizontal plane, effectively decoupling these two competing requirements.
Solution Approach 2:
The patent segments the device into distinct functional layers with specialized structures: photodetector regions optimized for light sensing, transistor regions for signal processing, and isolation structures positioned strategically between them. This segmentation allows each component to be optimized independently, enabling larger photodetector capacity without proportionally increasing overall pixel pitch.
3Length of moving object
If device scaling is pursued to reduce pixel pitch, then manufacturing precision requirements increase, but STI formation causes crystalline damage that limits further scaling
Solution Approach 1:
The patent removes the STI structure from the photodetector region, eliminating the complex substrate etching process that limits scaling. This extraction of the problematic manufacturing step allows for further reduction in pixel pitch without being constrained by the precision requirements and damage risks associated with deep STI etching at small dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables scaling down to a pixel pitch of less than 0.7 micrometers with improved photodetector capacity and charge transfer, while maintaining electrical isolation, thus enhancing the overall scaling and performance of the image sensor.
Implementation Method 1
The photodetector is configured to accumulate charge in response to incident radiation
Implementation Method 2
a doped well may be formed around the STI structure. The doped well passivates the crystalline damage to suppress the leakage/dark current
Data Source
AI summary
Various embodiments of the present disclosure are directed towards a stacked complementary metal-oxide semiconductor (CMOS) image sensor in which a pixel sensor spans multiple integrated circuit (IC) chips and is devoid of a shallow trench isolation (STI) structure at a photodetector of the pixel sensor. The photodetector and a first transistor form a first portion of the pixel sensor at a first IC chip. A plurality of second transistors forms a second portion of the pixel sensor at a second IC chip. By omitting the STI structure at the photodetector, a doped well surrounding and demarcating the pixel sensor may have a lesser width than it would otherwise have. Hence, the doped well may consume less area of the photodetector. This, in turn, allows enhanced scaling down of the pixel sensor.