3D Stacked CNT Memory Arrays with Nonlinear Selectors
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Solution Overview
Problem
Conventional carbon nanotube (CNT) memory devices are limited by their two-dimensional structure and underlying addressing circuitry, restricting their density and requiring complex fabrication processes.
Innovation Solution
A three-dimensional CNT memory stack is developed, using vertically stacked CNT memory devices with selector elements that are nonlinear resistors, such as amorphous silicon, to couple memory cells to bit lines, eliminating the need for diodes or transistors and allowing for independent fabrication in any semiconductor chip layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistors are used to select memory cells in a 2-D CNT memory array, then memory cells can be actively controlled, but memory cell density is limited by transistor density
Solution Approach 1:
The patent transitions from a two-dimensional memory array to a three-dimensional stacked memory architecture. Multiple CNT memory arrays are vertically stacked along the z-axis, allowing memory cells to be arranged in multiple layers. This dimensional change enables significantly higher memory cell density without being constrained by the planar limits of transistor fabrication, directly resolving the contradiction between control reliability and cell density.
Solution Approach 2:
The patent extracts and eliminates the transistor switching elements from the memory cell selection process. Instead of using transistors to select memory cells, the invention employs diode-based selection or direct electrical connection through word lines. This removal of the transistor component eliminates the bottleneck where memory cell density was limited by transistor density, while maintaining the ability to actively control and select individual memory cells.
2Quantity of substance
If diodes are used to replace transistor switches, then memory cell density can be reduced to less than 10 f2, but density is still limited by the 2-D structure and addressing circuitry
Solution Approach 1:
By stacking multiple memory arrays vertically to create a three-dimensional structure, the patent dramatically increases memory cell density beyond what is achievable in a two-dimensional planar structure. The vertical stacking allows multiple layers of memory cells to share common word lines and bit lines, reducing the overall addressing circuitry complexity while achieving densities exceeding 10 f2.
Solution Approach 2:
The patent implements word lines that serve multiple functions: they act as selection lines for memory cells in different vertical layers, provide common signal distribution across stacked arrays, and enable unified addressing control. This multi-functionality reduces the total amount of addressing circuitry needed compared to separate 2-D arrays, resolving the contradiction between high density and circuitry complexity.
3Reliability
If transistors are used for memory selection, then active control is achieved, but fabrication process becomes complex and integrated with underlying semiconductor devices
Solution Approach 1:
The patent extracts the memory selection function from the complex transistor-based switching network and implements it through simpler diode structures or direct electrical connections. This simplification decouples the memory device fabrication from the underlying semiconductor device manufacturing process, allowing independent fabrication and reducing overall manufacturing complexity while maintaining reliable memory cell selection control.
Solution Approach 2:
The patent introduces diode elements as intermediary components between the word lines and memory cells, providing a simpler alternative to transistor switches. These diodes serve as the selection mechanism while being easier to fabricate and integrate, thereby simplifying the overall manufacturing process while maintaining the reliability of active memory cell control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases memory device density, reduces power consumption, and simplifies fabrication by decoupling from underlying semiconductor devices, enabling on-demand memory additions and efficient use of silicon real estate.
Implementation Method 1
Each selector element is configured to couple a memory cell of the one or more memory cells to a respective bit line
Data Source
AI summary
A three-dimensional (3-D) memory stack and a method of formation thereof are described. The 3-D memory stack includes a number of vertically stacked memory devices. Each memory device includes one or more memory cells. Each of the memory cells can be formed on a conductive material. Each memory device further includes one or more selector elements each configured to couple a memory cell of the one or more memory cells to a respective bit line. None of the selector elements is configured as a diode or a transistor element.