Stacked Columnar ICs for Extended Cascade Length
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Solution Overview
Problem
The limited number of connections on an interposer in semiconductor devices restricts the maximum cascade length of cascade connections in stacked programmable integrated circuits (ICs), limiting their performance compared to a single large FPGA die.
Innovation Solution
The implementation of active-on-active 3D stacking, where two identical programmable IC dies are mounted face-to-face with electrical connections between them, allowing cascaded signals to form rings and increasing the maximum cascade length by enabling dense inter-die connections and efficient data recirculation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple smaller FPGA dies are mounted on an interposer, then manufacturing flexibility and heat dissipation are improved, but the maximum cascade length is reduced due to limited connections on the interposer
Solution Approach 1:
The patent transitions from 2D planar interposer connections to 3D vertical stacking with active-on-active mounting. By stacking dies vertically and using through-silicon vias for inter-die connections, the cascade length is extended in the vertical dimension, allowing cascade connections to span multiple dies without being constrained by the limited horizontal connection capacity of an interposer.
Solution Approach 2:
The patent embeds one FPGA die within another through vertical stacking, with the second die positioned directly on top of the first die. The cascade connections are nested through the inter-die interface, allowing signals to traverse from the first die, through the inter-die connection layer, and into the second die, effectively nesting the connection path within the stacked structure.
2Device complexity
If multiple smaller FPGA dies are mounted on an interposer, then device complexity is reduced through modular assembly, but the number of available connections is limited
Solution Approach 1:
The patent moves from 2D interposer-based connectivity to 3D vertical stacking, dramatically increasing the number of available connections. Through-silicon vias and active-on-active mounting enable dense inter-die connection networks that provide numerous parallel connection paths between stacked dies, far exceeding the connection capacity of traditional interposer architectures.
3Reliability
If cascade connections are embedded inside resource columns, then performance is guaranteed by design, but the cascade length is limited by the die boundary
Solution Approach 1:
The patent nests cascade connections within resource columns that span multiple stacked dies. Resource columns are vertically aligned across die boundaries, with embedded cascade connections passing through the inter-die interface. This nesting allows cascade signals to traverse the full height of the stacked structure while maintaining the performance guarantees of embedded connections, as the cascade logic is physically integrated within the resource column architecture rather than using external routing.
Data Source
AI summary
An example semiconductor device includes a first integrated circuit (IC) die including a first column of cascade-coupled resource blocks; a second IC die including a second column of cascade-coupled resource blocks, where an active side of the second IC die is mounted to an active side of the first IC die; and a plurality of electrical connections between the active side of the first IC and the active side of the second IC, the plurality of electrical connections including at least one electrical connection between the first column of cascade-coupled resource blocks and the second column of cascade-coupled resource blocks.