Stacked Command Queue for Memory Controller Arbitration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As DRAMs increase in size and complexity, memory controllers face challenges in optimizing memory access efficiency without excessive size and cost, and they must handle higher performance demands from multiple processing cores, making it difficult to manage memory access requests effectively.
Innovation Solution
A memory controller design that includes a command queue with stacked entry stacks, an arbiter, and a command queue loader circuit, which loads and arbitrates memory access commands efficiently, using common characteristics to select commands for transmission to DRAM, optimizing memory bus usage and handling flow control credits to improve performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If DRAM size and complexity increase, then memory capacity and features improve, but memory controller size and cost increase excessively
Solution Approach 1:
The command queue is divided into multiple entry stacks, each handling specific memory access commands. This segmentation allows the memory controller to process commands in organized groups, reducing the complexity of managing individual commands while supporting increased DRAM capacity and multiple memory clients.
Solution Approach 2:
The patent introduces a stacked command queue architecture that adds a vertical dimension to command organization. Instead of a simple linear queue, commands are arranged in multiple stacks with head indicators, creating a multi-dimensional command management structure that improves efficiency without proportionally increasing controller complexity.
2Adaptability or versatility
If number of memory clients increases, then system complexity improves, but memory access efficiency deteriorates
Solution Approach 1:
The command queue is segmented into multiple entry stacks that can independently manage commands from different memory clients. Each stack can be arbitrates separately, allowing the memory controller to efficiently handle requests from multiple processing cores and memory clients simultaneously without degradation in access efficiency.
Solution Approach 2:
Commands from multiple memory clients are pre-organized into separate entry stacks before arbitration. This preliminary organization allows the arbiter to efficiently select commands from appropriate stacks based on current memory state, reducing arbitration complexity and maintaining high access efficiency even with increased numbers of memory clients.
3Ease of manufacture
If conventional command queue is used, then implementation is simple, but memory bus utilization is insufficient
Solution Approach 1:
The patent transforms the conventional linear command queue into a stacked queue structure with multiple entry stacks and head indicators. This dimensional change enables more sophisticated command scheduling and arbitration, significantly improving memory bus utilization by allowing selective access to different command stacks based on current memory conditions while maintaining reasonable implementation complexity.
Solution Approach 2:
The stacked command queue architecture introduces dynamic command selection capabilities. The arbiter can dynamically choose which entry stack to service based on real-time memory state, command types, and client priorities. This dynamic behavior optimizes memory bus utilization by selecting the most appropriate commands for execution at each moment.
Data Source
AI summary
A memory controller includes a command queue with multiple entry stacks, each with a plurality of entries holding memory access commands, one or more parameter indicators each holding a respective characteristic common to the plurality of entries, and a head indicator designating a current entry for arbitration. An arbiter has a single command input for each entry stack. A command queue loader circuit receives incoming memory access commands and loads entries of respective entry stacks with memory access commands having the respective characteristic of each of the one or more parameter indicators in common.