Stacked Common Gate FinFETs for Area Optimization
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Solution Overview
Problem
There is a need to reduce the size and area footprint of standard cells in integrated circuits, such as ASICs and SoC devices, as they often contain thousands to millions of cells, and existing technologies have not effectively optimized the layout to achieve this.
Innovation Solution
The proposed solution involves a metal oxide semiconductor (MOS) device with a stacked configuration of FinFETs, where two FinFETs share a gate interconnect, and their fins are connected in a specific manner to form sources and drains, allowing for a reduced footprint while maintaining functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If FinFETs are stacked in a shared-gate configuration to reduce area footprint, then the area of the MOS device is reduced, but the time delay increases and drive strength decreases
Solution Approach 1:
The patent divides a single FinFET into multiple stacked FinFETs (first FinFET and second FinFET) that share a common gate. Each FinFET has its own source and drain regions, creating segmented current paths that reduce the horizontal area footprint while stacking vertically. The gate interconnect serves both FinFETs, further reducing area compared to separate gates.
Solution Approach 2:
The patent transitions from a planar FinFET layout to a vertically stacked configuration. By stacking FinFETs in the vertical dimension rather than placing them side-by-side in the horizontal plane, the area footprint is reduced. The shared gate extends vertically to control multiple FinFET stacks, utilizing the third dimension (vertical stacking) to achieve area optimization.
2Area of stationary object
If FinFETs are stacked in a shared-gate configuration to reduce area footprint, then the area of the MOS device is reduced, but the drive strength decreases
Solution Approach 1:
The patent segments the transistor function into multiple stacked FinFETs with separate source and drain regions. Each FinFET contributes to the overall drive strength, and the segmented configuration allows for optimized current paths through individual interconnects (first interconnect, second interconnect, third interconnect) that connect to respective sources and drains.
Solution Approach 2:
By moving to vertical stacking, the patent increases the effective channel width in the vertical dimension while reducing horizontal footprint. The shared gate controls multiple FinFETs stacked vertically, effectively multiplying the drive strength contribution per unit area compared to planar configurations.
Data Source
AI summary
A MOS device includes a first FinFET having a first transistor source, drain, gate, and set of fins, and includes a second FinFET having a second transistor source, drain, gate, and set of fins. The MOS device further includes a gate interconnect extending linearly to form and to connect together the first and second transistor gates. The MOS device further includes a first interconnect on a first side of the gate interconnect that connects together the set of first transistor fins at the first transistor drain and the set of second transistor fins at the second transistor source, a second interconnect on a second side of the gate interconnect that connects together the set of first transistor fins at the first transistor source, and a third interconnect on the second side of the gate interconnect that connects together the set of second transistor fins at the second transistor drain.