Stacked Complementary FET Fabrication for Higher Transistor Density
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Solution Overview
Problem
Current methods for manufacturing semiconductor devices with a complementary FET structure face challenges in increasing the number of transistors per area of a substrate, including misalignment issues, increased process complexity, and higher costs due to the need for multiple layers and additional processing steps.
Innovation Solution
A method involving the formation of laminated films with N-type and P-type channels on separate substrates, followed by bonding and removing these substrates to create a vertically stacked complementary FET structure, allowing for simultaneous formation of sources, drains, and gates on both surfaces, thereby optimizing channel and contact materials and reducing misalignment and process complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple layers and additional processing steps are used to form complementary FET structure, then the transistor functionality is achieved, but the manufacturing complexity and cost increase
Solution Approach 1:
The manufacturing process is divided into two independent stages: first forming N-type channel structures on a first substrate, then bonding a second substrate with P-type channel structures. This segmentation allows each transistor type to be manufactured separately using optimized processes, reducing overall manufacturing complexity while achieving the complementary FET structure.
Solution Approach 2:
A bonding substrate is introduced as an intermediary element to facilitate the connection between N-type and P-type channel structures. The bonding substrate enables precise alignment and bonding of the two separate transistor structures without requiring complex multi-layer fabrication processes, thereby reducing manufacturing complexity.
2Productivity
If traditional methods are used to increase transistor density, then area utilization improves, but misalignment issues and process complexity increase
Solution Approach 1:
By separating the fabrication of N-type and P-type transistors into independent stages on separate substrates, the method achieves high transistor density through vertical stacking while avoiding misalignment issues. Each substrate can be processed independently with standard alignment procedures, eliminating the cumulative alignment errors that would occur in traditional multi-layer approaches.
3Productivity
If vertically stacked structure is formed, then the number of transistors per area increases, but the manufacturing process becomes more complex
Solution Approach 1:
The vertically stacked complementary FET structure is achieved by segmenting the manufacturing into two independent processes: forming N-type channels on a first substrate and forming P-type channels on a second substrate. This segmentation allows each transistor type to be manufactured using standard, well-established processes, reducing the overall manufacturing complexity despite the advanced three-dimensional architecture.
Solution Approach 2:
The bonding substrate serves as an intermediary that enables the connection of two separately manufactured transistor structures. This intermediary approach simplifies the manufacturing process by allowing independent optimization of each transistor type's fabrication while achieving the desired vertical integration for high transistor density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the density of transistors per area, simplifies the wiring process, and reduces the number of processing steps, while allowing for optimal material selection for N-type and P-type channels, thus improving the structural flexibility and efficiency of the semiconductor device manufacturing.
Implementation Method 1
a step of forming a laminated film by laminating an N-type channel and a P-type channel on a substrate
Implementation Method 2
a step of bonding a new substrate on the front surface side
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a laminated film by laminating an N-type channel and a P-type channel on a substrate; performing patterning on the laminated film; forming a source and a drain on a front surface side; bonding a new substrate on the front surface side and removing the substrate on a back surface side; forming a source and a drain on the back surface side; and a step of forming a gate on the back surface side.