Stacked Active Components in Multilayer Wiring Boards for Smaller Packages
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Solution Overview
Problem
Existing semiconductor device technologies face challenges in further reducing size due to limitations in wire bonding and component stacking, leading to increased component arrangement areas and reduced efficiency in utilizing internal space.
Innovation Solution
A semiconductor device with a multilayer wiring board and stacked active components, where a first active component is on one surface and a second active component with a smaller planar area is closer to the external connection terminal, connected via a connection via, allowing efficient internal component arrangement and reduced size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is used to connect electronic components, then electrical connection is achieved, but device size cannot be further reduced due to required wire bonding region
Solution Approach 1:
The patent transitions from planar wire bonding connections to three-dimensional stacked component arrangement with vertical via connections. Multiple active components are stacked in the thickness direction and connected through connection vias, eliminating the need for lateral wire bonding regions and enabling compact device integration.
Solution Approach 2:
The patent implements nested arrangement where smaller planar area components are positioned within the projection area of larger components in the stacking direction. This nested doll-like configuration maximizes space utilization and reduces the overall device footprint while maintaining all necessary electrical connections through vertical vias.
2Ease of manufacture
If electronic components are arranged in parallel, then electrical connection is simplified, but component arrangement area increases
Solution Approach 1:
The patent arranges multiple active components in the thickness direction (stacked configuration) rather than in parallel on the same plane. Connection vias provide vertical electrical pathways between stacked components, achieving simplified connections while dramatically reducing the planar arrangement area required for component placement.
Solution Approach 2:
The patent employs flexible routing through connection vias that can dynamically adapt to different component stacking configurations. The via-based connection system allows components to be positioned in three-dimensional space rather than constrained to fixed planar positions, enabling optimized space utilization.
3Ease of manufacture
If uniform sized components are stacked, then manufacturing is simplified, but internal space utilization efficiency decreases
Solution Approach 1:
The patent applies different planar areas to different active components based on their functional requirements and positions in the stack. Components closer to the front surface have smaller planar areas, while components toward the rear surface have larger planar areas. This localized differentiation optimizes space utilization while maintaining manufacturing feasibility through standardized via connections.
Data Source
AI summary
To provide a semiconductor device further reduced in size. A semiconductor device including: a multilayer wiring board one surface of which is provided with an external connection terminal; and a plurality of active components that are provided to be stacked inside the multilayer wiring board and are connected to the external connection terminal via a connection via. The plurality of active components include a first active component provided on another surface side that is opposite to the one surface, and a second active component that is provided closer to the one surface than the first active component is and has a smaller planar area than the first active component.