Stacked Compound Semiconductor IC with Cu-Au Metal Layers
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Solution Overview
Problem
The integration of multiple circuit elements on a single compound semiconductor MMIC chip leads to high process costs and low yield due to complex integration, resulting in large module sizes and significant signal loss and interference from long interconnections.
Innovation Solution
A semiconductor integrated circuit design featuring stacked chips, where at least one chip is a compound semiconductor chip, with a metal layer forming connections between chips to reduce interconnection length and prevent signal loss, using Au for direct contact with semiconductor devices and Cu for interconnections to avoid contamination and maintain reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple circuit elements are integrated on one compound semiconductor MMIC chip, then circuit functionality is improved, but process cost increases and manufacturing yield decreases
Solution Approach 1:
The patent divides the integrated circuit system into multiple separate chips, each containing specific circuit elements. These chips are then stacked vertically and interconnected through conductive via holes, replacing the conventional approach of integrating all elements on a single chip. This segmentation reduces manufacturing complexity and cost while maintaining full circuit functionality across the stacked architecture.
2Adaptability or versatility
If multiple circuit elements are integrated on one compound semiconductor MMIC chip, then circuit functionality is improved, but manufacturing yield decreases
Solution Approach 1:
By segmenting the circuit into multiple separate chips that can be manufactured independently using optimized processes for each chip type, the patent improves manufacturing yield. Each chip can be fabricated with process parameters tailored to its specific requirements, avoiding the yield penalties associated with integrating diverse circuit elements on a single complex chip.
3Ease of operation
If chips are placed in one plane, then ease of assembly is improved, but module size increases
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement of chips to a three-dimensional stacked configuration. Multiple chips are arranged vertically and interconnected through conductive via holes, enabling compact module sizing while maintaining assembly feasibility through standardized stacking and bonding processes.
4Ease of operation
If chips are placed in one plane, then ease of assembly is improved, but interconnection length increases causing signal loss
Solution Approach 1:
By stacking chips vertically and interconnecting them through conductive via holes, the patent dramatically reduces interconnection length compared to planar arrangements. The vertical stacking architecture enables direct through-silicon vias and short inter-chip bonds, minimizing signal path length and reducing energy loss while maintaining assembly simplicity.
5Ease of manufacture
If all metal layers are made of Cu, then manufacturing cost is reduced, but contamination of semiconductor devices occurs
Solution Approach 1:
The patent implements a differentiated metal layer strategy where Cu is used for cost-effective interconnection layers that do not contact semiconductor devices, while Au is used for metal layers requiring direct contact with devices to prevent contamination. This local quality differentiation optimizes both manufacturing cost and device reliability by assigning appropriate materials to specific functional locations.
6Ease of operation
If long interconnections are used between chips, then ease of connection is improved, but signal loss and interference increase
Solution Approach 1:
The patent uses vertical stacking with conductive via holes to create short, direct interconnections between chips. This three-dimensional architecture replaces long planar interconnections with compact vertical pathways, significantly reducing signal loss and electromagnetic interference while maintaining connection ease through standardized via and bonding processes.
Data Source
AI summary
The present invention relates to a compound semiconductor integrated circuit chip having a front and/or back surface metal layer used for electrical connection to an external circuit. The compound semiconductor integrated circuit chip (first chip) comprises a substrate, an electronic device layer, and a dielectric layer. A first metal layer is formed on the front side of the dielectric layer, and a third metal layer is formed on the back side of the substrate. The first and third metal layer are made essentially of Cu and used for the connection to other electronic circuits. A second chip may be mounted on the first chip with electrical connection made with the first or the third metal layer that extends over the electronic device in the first chip in the three-dimensional manner to make the electrical connection between the two chips having connection nodes away from each other.