Stacked Conductive Pattern Structure for Delamination-Resistant Memory
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Solution Overview
Problem
High-speed and low-voltage semiconductor memory devices require improved integration density and reliability, but existing technologies face challenges in enhancing adhesion between conductive patterns and insulating layers to prevent delamination and cracking.
Innovation Solution
A semiconductor device design featuring conductive structures with roughened side surfaces and specific barrier and insulating layers to increase contact areas and adhesion, including upper and lower conductive patterns with overlapping areas covered by barrier and insulating layers, enhancing the reliability by preventing delamination and cracking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional smooth conductive patterns are used, then manufacturing is simpler, but adhesion between conductive and insulating layers is insufficient causing delamination and cracking
Solution Approach 1:
The patent merges the lower conductive pattern and upper conductive pattern to form an integrated conductive structure with overlapping regions. This combined structure provides enhanced adhesion area between conductive and insulating layers, preventing delamination and cracking while maintaining manufacturing feasibility through a unified formation process
Solution Approach 2:
The patent transitions from planar conductive patterns to a three-dimensional stacked structure with vertical overlap. The upper conductive pattern is positioned vertically above the lower conductive pattern, creating additional adhesion interfaces in the vertical dimension that prevent delamination without complicating the horizontal manufacturing process
2Productivity
If integration density is increased to meet high-speed and low-voltage demands, then device performance improves, but reliability decreases due to increased risk of delamination and cracking
Solution Approach 1:
The patent implements a nested structure where the upper conductive pattern is vertically nested above the lower conductive pattern with overlapping regions. This nested arrangement increases integration density by utilizing vertical space while the overlapping portions provide redundant adhesion areas that prevent delamination and cracking under high-density conditions
Solution Approach 2:
The patent creates a composite conductive structure combining lower and upper conductive patterns with insulating layers in between. This composite structure provides both high integration density through vertical stacking and enhanced reliability through multiple adhesion interfaces between different material layers, preventing delamination and cracking
Data Source
AI summary
A semiconductor device comprising: a substrate; and a conductive structure on the substrate, wherein the conductive structure comprises: a lower conductive structure comprising a lower conductive pattern; and an upper conductive structure comprising an upper conductive pattern, wherein the upper conductive structure is on the lower conductive structure, wherein at least one of a first side surface of the lower conductive pattern or a second side surface of the upper conductive pattern comprises a rough surface, and wherein a first width of a lower surface of the upper conductive pattern in a first direction parallel to a lower surface of the substrate is substantially equal to or less than a second width of an upper surface of the lower conductive pattern in the first direction.