Stacked Conductive Patterns in Display Devices to Reduce Bezel Area
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Solution Overview
Problem
Existing display devices face challenges in reducing the non-display area (bezel area) to minimize size and weight, as connection lines occupy significant space within the display area.
Innovation Solution
The display device employs a novel design with overlapping conductive patterns and active patterns, utilizing contact holes to bypass gate signals and eliminate fan-out lines, allowing additional space for conductive patterns without increasing the non-display area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional conductive patterns and fan-out lines are used to route gate signals and data voltages, then the display device can function properly, but the non-display area (bezel area) increases
Solution Approach 1:
The patent combines multiple conductive patterns (gate lines and data lines) into overlapping configurations where the same physical space serves multiple routing functions. The first and second conductive patterns are disposed at different locations but overlap in certain regions, allowing gate signals and data voltages to be routed through shared spatial pathways, thereby eliminating the need for separate fan-out lines and reducing the non-display area.
Solution Approach 2:
The patent utilizes vertical stacking of conductive patterns at different locations (first conductive pattern and second conductive pattern disposed at different locations) to route multiple signals through overlapping two-dimensional planes. This multi-layer approach allows gate lines and data lines to coexist in the same planar region without interference, effectively using the third dimension (vertical layering) to resolve spatial conflicts and minimize the bezel area.
2Area of stationary object
If the display area is enlarged to reduce device size, then the non-display area decreases, but routing connection lines becomes more difficult
Solution Approach 1:
By merging the routing paths of gate lines and data lines into overlapping configurations, the patent simplifies the overall connection architecture. The first gate line and second gate line, along with data lines, are routed through shared overlapping regions, reducing the total number of separate routing channels needed and making the enlarged display area layout more manageable.
Solution Approach 2:
The patent resolves routing complexity in enlarged displays by utilizing vertical layering of conductive patterns. Multiple connection lines are routed through different vertical layers that overlap in the planar view, allowing complex signal distributions across large display areas without increasing planar routing complexity.
Data Source
AI summary
A display device includes a first active pattern, a first conductive pattern including a gate electrode overlapping the first active pattern, a first gate line overlapping the first active pattern and extending in a first direction, and a second gate line extending in the first direction, a second conductive pattern disposed on the first conductive pattern and including a third gate line extending in the first direction and a fourth gate line extending in the first direction, a second active pattern disposed on the second conductive pattern and including a material different from a material of the first active pattern, and a third conductive pattern disposed on the second active pattern and including a first upper electrode overlapping the third gate line and connected to the third gate line, and a second upper electrode overlapping the fourth gate line and connected to the fourth gate line.