Stacked Conductive Sub-Patterns for Display Substrates

The patent divides the single thick copper wire structure into multiple stacked conductive sub-patterns (first conductive sub-pattern, second conductive sub-pattern, etc.) with buffer layers between them. Each sub-pattern can be formed with controlled thickness, and the stress from each layer can be independently managed through the buffer layers, preventing cumulative stress from causing substrate bending or breakage while maintaining low overall resistance through the stacked conductive paths.

The patent introduces buffer layers (first buffer layer, second buffer layer, etc.) as intermediary structures between adjacent conductive sub-patterns. These buffer layers serve as stress-absorbing intermediaries that prevent direct stress transmission between the rigid copper layers and the substrate, allowing stress to be distributed and managed without causing substrate deformation or failure.

The patent segments the thick copper wire into multiple thinner conductive sub-patterns stacked vertically. This segmentation reduces the stress imposed on the substrate by any single layer, preventing substrate bending or breakage while maintaining electrical conductivity through the stacked configuration. The substrate strength is preserved because no single layer creates excessive localized stress.

The buffer layers act as protective intermediaries between the conductive sub-patterns and the substrate, absorbing and distributing mechanical stress to prevent substrate damage. This intermediary structure preserves substrate integrity by preventing direct stress concentration that would cause bending or breakage.

The patent merges multiple patterning steps into a unified manufacturing flow where buffer layers and conductive sub-patterns are formed in an integrated sequence. The buffer layers serve dual purposes: electrical isolation and stress management. This merging of functions reduces the number of separate process modules needed, managing manufacturing complexity while achieving the desired stress distribution and substrate integrity.

The buffer layers are designed to perform multiple functions simultaneously: providing electrical isolation between conductive sub-patterns, managing stress distribution, and serving as etch stop layers. This multi-functionality reduces the need for additional dedicated structures, simplifying the overall manufacturing process while maintaining substrate integrity.