Stacked Conductive Vias for High-Density Capacitor Isolation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The challenge in achieving high integration density of electronic elements, such as capacitors, is exacerbated by the risk of short circuits between conductive vias due to large critical dimensions and high aspect ratios during the etching process, which complicates the manufacturing process and reduces yield.

Innovation Solution

A conductive structure is designed with stacked conductive vias, where the lateral surfaces of the vias are discontinuous, and a method involving multiple support layers and selective etching is used to form these vias, reducing the aspect ratio and minimizing the risk of short circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the critical dimension of the hole is increased to reduce under etch risk, then the manufacturing reliability is improved, but the risk of short between adjacent conductive vias increases

Engineering Contradiction:
Improvemanufacturing reliabilityVSAvoidshort circuit risk
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The conductive via structure is segmented into multiple sections with different lateral dimensions. The via includes a first section with a first lateral dimension and a second section with a second lateral dimension that is smaller than the first lateral dimension. This segmentation allows the upper portion to have a larger width for better etch control while the lower portion has a smaller width to prevent short circuits with adjacent vias.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different sections of the conductive via have different local dimensions optimized for their specific functions. The first section (upper portion) has a larger lateral dimension to reduce under etch risk during manufacturing, while the second section (lower portion) has a smaller lateral dimension to prevent short circuits. This local quality variation resolves the contradiction between manufacturing reliability and short circuit prevention.

Inventive Principle:
Principle #3Local quality

2Productivity

If the aspect ratio of the conductive via is increased to achieve high integration density, then the productivity is improved, but the manufacturing precision deteriorates

Engineering Contradiction:
Improveintegration densityVSAvoidvia dimension control
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The via is divided into multiple sections with different aspect ratios. The first section has a smaller aspect ratio making it easier to manufacture with precise dimension control, while the second section has a larger aspect ratio enabling higher integration density. This segmentation allows the overall structure to achieve high productivity while maintaining manufacturing precision in critical areas.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The via structure transitions from a single uniform dimension to a multi-dimensional structure with varying lateral dimensions at different depths. This dimensional variation allows the via to achieve both high aspect ratio (for productivity/integration density) and precise dimension control (for manufacturing precision) by having different widths at different sections.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12431425B2Conductive structure and capacitor structure and method for manufacturing the same
Publication Date: 2025.09.30 NAN YA TECH
  • US12431425B2 patent drawing
  • US12431425B2 patent drawing
  • US12431425B2 patent drawing

AI summary

A conductive structure and a capacitor structure and a method of manufacturing a conductive structure are provided. The conductive structure includes a first support layer, a second support layer, a first conductive via, a third support layer and a second conductive via. The second support layer is disposed over the first support layer. The first conductive via is disposed between the first support layer and the second support layer. The third support layer is disposed over the second support layer. The second conductive via is disposed between the second support layer and the third support layer, and electrically connected to the first conductive via. A lateral surface of the first conductive via is discontinuous with a lateral surface of the second conductive via.