Stacked Conductor Layout for NAND Voltage Isolation
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high integration and large capacity while maintaining efficient voltage application and insulation between conductors, particularly in NAND flash memory devices.
Innovation Solution
A semiconductor device design with a stacked wiring structure and specific conductor arrangements, including conductors aligned with varying pitches and insulation configurations to manage voltage differences and prevent breakdown, is employed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple wirings are arranged in the same layer for high integration, then integration and capacity are improved, but voltage application and insulation between conductors become more difficult to maintain
Solution Approach 1:
The patent transitions from planar wiring arrangement to a three-dimensional stacked structure where conductors are arranged in multiple layers vertically. This dimensional change allows multiple conductors to coexist without planar interference, maintaining insulation while achieving high integration. The stacked configuration with alternating conductive layers and insulating layers resolves the conflict between density and electrical isolation.
Solution Approach 2:
The patent segments the conductor arrangement into distinct stacked layers with insulating material between them. Each conductor layer is separated by insulating layers, creating discrete electrical zones. This segmentation maintains voltage application integrity while allowing multiple conductors to be packed closely in the vertical dimension, thus improving integration without compromising insulation reliability.
2Reliability
If conductors are arranged with varying pitches for optimization, then performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent introduces insulating layers as intermediary structures between conductors with different pitches. These insulating layers act as buffer zones that accommodate pitch variations without direct mechanical or electrical contact between conductors. The intermediary insulating material absorbs alignment tolerances, reducing the stringency of manufacturing precision requirements while maintaining optimal electrical performance.
3Quantity of substance
If conductors are placed closer together for high integration, then capacity is improved, but risk of breakdown increases
Solution Approach 1:
The patent employs insulating layers as intermediary barriers between closely spaced conductors. These insulating layers prevent direct electrical contact and field interaction that could lead to breakdown. By introducing this intermediary material, the patent achieves high conductor density for improved capacity while the insulating barriers mitigate the harmful effects of close spacing, preventing breakdown even at reduced pitch.
Data Source
AI summary
According to one embodiment, a semiconductor device includes: a control circuit provided on a substrate; and a plurality of conductors provided in a first layer positioned away from the substrate in a first direction. The plurality of conductors include first, second, third, and fourth conductors arranged in this order in a second direction. The control circuit is configured to: apply, in a case of applying a first voltage to the first conductor, a second voltage different from the first voltage to the third and fourth conductors; and be insulated from the second conductor. The third and fourth conductors are aligned in the second direction with a first pitch. The first, second, and third conductors are aligned in the second direction with a second pitch equal to or less than the first pitch.