Stacked Semiconductor Connection Structure for Ion Diffusion Isolation
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Solution Overview
Problem
Semiconductor devices face challenges with high production costs and low yield rates due to defects, particularly in three-dimensional structures like three-dimensional NAND flash memory, which need improvements for enhanced efficiency and reliability.
Innovation Solution
A semiconductor device design featuring a stacked structure with alternating metal and spacer layers, a connection structure including a metal core, metal oxide layer, and barrier layer, and a first insulation layer, where the metal oxide and barrier layer surfaces are not equal in height, and the insulation layer is in direct contact with the metal core, preventing ion diffusion and reducing electrical leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a connection structure with metal core is used to run through the stacked structure, then electrical connectivity is improved, but metal ion diffusion to the metal oxide layer occurs causing performance degradation
Solution Approach 1:
A barrier layer is introduced as an intermediary between the metal core and metal oxide layer. This barrier layer prevents metal ions from diffusing from the metal core to the metal oxide layer, thereby maintaining the performance and reliability of the metal oxide layer while preserving electrical connectivity through the metal core.
Solution Approach 2:
The connection structure employs a composite material architecture consisting of multiple layers: metal core, barrier layer, and metal oxide layer. Each layer serves a specific function - the metal core provides electrical conductivity, the barrier layer prevents ion diffusion, and the metal oxide layer provides insulation and structural stability. This composite structure resolves the contradiction between electrical connectivity and prevention of harmful ion diffusion.
2Quantity of substance
If metal cores are placed close together in the stacked structure, then device density is improved, but electrical leakage between metal cores increases
Solution Approach 1:
The first insulation layer acts as an intermediary between adjacent metal cores, providing electrical isolation that prevents leakage current while allowing the metal cores to be positioned closely together. This enables high device density without compromising electrical performance.
Solution Approach 2:
A thin film insulation layer is applied to the sidewalls of the metal cores. This thin film provides effective electrical isolation between adjacent cores while occupying minimal space, thereby enabling high device density without electrical leakage.
3Quantity of substance
If feature sizes are reduced to increase device capacity, then storage capacity is improved, but production cost increases and yield rate decreases
Solution Approach 1:
The patent applies different material properties to different regions of the device. The barrier layer and insulation layers are strategically positioned at critical interfaces where ion diffusion and electrical leakage are most problematic. This localized quality enhancement allows for reduced feature sizes without proportionally increasing defect rates, thereby improving storage capacity while maintaining acceptable yield rates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances insulation performance by preventing metal ion diffusion and reducing electrical leakage, thereby improving the overall performance and reliability of the semiconductor device.
Implementation Method 1
The barrier layer can prevent diffusion of metal ions inside the metal core to the metal oxide layer
Implementation Method 2
The first insulation layer is in direct contact with the sidewall of the metal core to isolate the metal cores from each other, which can reduce leakage of electricity of the metal core
Data Source
AI summary
The present application provides a semiconductor device and a manufacturing method for the semiconductor device, which relates to the field of semiconductor technology, for solving a technical problem of poor device performance. The semiconductor device includes a stacked structure, a connection structure, and a first insulation layer, where the connection structure runs through the stacked structure, and includes a metal core located inside the stacked structure, a metal oxide layer located on a sidewall of the metal core, and a barrier layer located between the metal oxide layer and the metal core. A top surface of the metal oxide layer and a top surface of the barrier layer are not equal in height and the metal oxide layer is in direct contact with the stacked structure. The first insulation layer is in direct contact with the sidewall of the metal core.