Stacked Connector Pin Routing for EMI Reduction
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Solution Overview
Problem
The existing standard for QSFP/QSFP+/zQSFP+ connectors, which routes all pins to the bottom of the connector housing, leads to increased EMI leakage and difficulty in routing high-speed conductive traces on circuit boards due to the proximity of low-speed pins, resulting in higher manufacturing costs and potential crosstalk.
Innovation Solution
Rerouting low-speed signal pins to the back side and high-speed signal pins to the bottom side of the connector housing, allowing for separate mounting areas on the circuit board and reducing EMI leakage, which simplifies trace routing and decreases the number of layers needed for high-speed conductive traces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If all pins are routed to the bottom of the connector housing, then the connector structure is simplified, but EMI leakage increases and trace routing becomes difficult
Solution Approach 1:
The patent segments the pin routing into two separate groups: high-speed signal pins are routed to the bottom of the housing, while low-speed signal pins are routed to the back side. This segmentation separates the routing paths of different signal types, reducing EMI leakage and simplifying trace routing on the circuit board.
2Device complexity
If low-speed pins are located near high-speed pins, then the connector layout is simplified, but crosstalk increases and trace routing becomes difficult
Solution Approach 1:
The patent segments the pin locations into separate groups based on signal speed requirements. Low-speed pins are positioned on the back side of the housing, while high-speed pins are positioned on the bottom side. This spatial segmentation creates physical separation between low-speed and high-speed signal paths, reducing crosstalk and simplifying circuit board trace routing.
3Ease of manufacture
If all pins are routed to the bottom side, then manufacturing is simplified, but the number of layers needed for high-speed traces increases
Solution Approach 1:
The patent segments the pin routing destinations into two separate locations: bottom side for high-speed pins and back side for low-speed pins. This segmentation allows high-speed traces to be routed on fewer layers since they are concentrated in one area, while low-speed traces can be routed separately without interfering with high-speed signal integrity.
Data Source
AI summary
A stacked connector component includes a housing, connectors at a front opening of the housing and arranged in a stacked formation within one or more columns, and a for and exposed at the connectors. The pins include high-speed pins routed within the housing to a bottom side thereof and low-speed pins routed within the housing to a back side or a top side thereof. A circuit board includes pin pads connectable to the pins and disposed on a substrate. The pin pads include high-speed signal pin pads for the high-speed signal pins. The substrate includes contiguous high-speed areas in which the high-speed signal pin pads for the high-speed pins are located, between which no pin pads are located.