Stacked Source/Drain Contact Structures for Carrier Mobility
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Solution Overview
Problem
The existing stacked semiconductor devices require performance improvements, particularly in terms of device density and efficiency, despite the introduction of backside power distribution networks.
Innovation Solution
The formation of source/drain patterns and corresponding contact structures with specific structural characteristics at different levels, including recesses and varying materials, to enhance channel stresses and improve device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional source/drain contact structures are used in stacked semiconductor devices, then manufacturing is simpler, but device performance and carrier mobility are insufficient
Solution Approach 1:
The contact structure is divided into multiple segments: a first contact structure at the first level and a second contact structure at the second level. Each contact structure has distinct structural characteristics (e.g., different recess depths, different material compositions) optimized for their respective transistor types (n-type and p-type), allowing independent optimization of carrier mobility for each segment without compromising the other.
Solution Approach 2:
Different regions of the contact structure are assigned different local qualities: the first contact structure may have a deeper recess and different doping concentration optimized for n-type transistors, while the second contact structure has characteristics optimized for p-type transistors. This local differentiation maximizes carrier mobility in each region according to the specific electrical requirements of the underlying transistor type.
2Reliability
If uniform contact structures are used across all levels, then manufacturing is easier, but channel stress and carrier mobility are not optimized
Solution Approach 1:
The contact structure transitions from a static, uniform design to a dynamic, differentiated design where structural parameters (recess depth, material composition, doping concentration) vary by level. This dynamic approach allows each contact structure to adapt its characteristics to the specific requirements of the transistor type it serves, optimizing carrier mobility through tailored mechanical and electrical properties at each level.
Solution Approach 2:
Key parameters of the contact structure are changed across different levels: recess depth, material composition, and doping concentration are adjusted to optimize performance. For example, the first contact structure may have a deeper recess and higher doping concentration than the second contact structure, creating parameter differentiation that enhances carrier mobility for each transistor type while maintaining manufacturability through systematic parameter variation.
3Reliability
If deeper recesses are formed in source/drain patterns, then channel stress increases and carrier mobility improves, but manufacturing precision requirements increase
Solution Approach 1:
The recess formation process is segmented into level-specific operations: a first recess is formed in the first source/drain pattern at the first level, and a second recess is formed in the second source/drain pattern at the second level. Each recess has depth and dimensions optimized for its specific transistor type, allowing precise control of channel stress without requiring a single ultra-precise recess formation process for all levels.
Solution Approach 2:
Each recess is given local quality appropriate to its function: the first recess may be deeper and narrower to maximize stress in n-type transistors, while the second recess may be shallower and wider for p-type transistors. This local optimization of recess geometry allows each contact structure to achieve sufficient channel stress with manufacturing precision requirements that are realistic for each specific level rather than requiring maximum precision across all levels.
Data Source
Figure 1
Figure 2A
Figure 2B~2C
AI summary
Provided is a semiconductor device which includes: a 1st source/drain pattern at a 1st level; a 2nd source/drain pattern at a 2nd level vertically different from the 1st level; and a 1st contact structure on the 1st source/drain pattern, wherein a portion of the 1st source/drain pattern is in a 1st recess of the 1st contact structure.