Stacked Multi-Gate Contacts With Selective Silicide for Low Resistance

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Solution Overview

Problem

Existing complementary field effect transistor (C-FET) structures face challenges in reducing contact resistance due to the increase in contact length and decrease in contact area, particularly when forming source/drain contacts in stacked multi-gate device configurations.

Innovation Solution

The method involves selectively depositing a first silicide layer on p-type source/drain features using metal precursors selective to silicon germanium surfaces or by using a self-assembled monolayer blocking layer on germanium-free surfaces, followed by the global deposition of an n-type dipole layer and a second silicide layer to reduce contact resistance with both p-type and n-type source/drain features.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If stacked multi-gate device configurations are used to increase device density, then device density is improved, but contact resistance increases due to increased contact length and decreased contact area

Engineering Contradiction:

Improvedevice densityVSAvoidcontact resistance

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent applies different silicide materials to different contact regions based on the underlying semiconductor type. Titanium silicide is used for n-type source/drain contacts while cobalt silicide is used for p-type source/drain contacts. This local differentiation optimizes contact resistance for each specific region, addressing the worsening contact resistance issue while maintaining high device density in stacked configurations.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent changes the material composition parameter of the silicide layer based on the contact region requirements. By selecting different metal precursors (titanium vs. cobalt) and controlling deposition conditions, the patent achieves optimal contact resistance values for both n-type and p-type contacts in stacked devices, thereby resolving the contact resistance problem without sacrificing device density.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If selective silicide deposition is performed on p-type source/drain features, then contact resistance for p-type contacts is reduced, but process complexity increases due to selective deposition requirements

Engineering Contradiction:

Improvecontact resistanceVSAvoidprocess complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent performs preliminary selective deposition of titanium silicide on n-type source/drain features before depositing cobalt silicide on p-type features. This preliminary action with titanium silicide creates a foundation that simplifies subsequent processing steps. The selective deposition sequence is carefully planned and executed to reduce overall process complexity while achieving the desired contact resistance reduction for both contact types.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent segments the silicide deposition process into distinct stages: first depositing titanium silicide on n-type regions, then cobalt silicide on p-type regions. This segmentation allows each deposition step to be optimized independently, reducing the complexity of attempting to deposit both silicides simultaneously. The segmented approach makes the selective deposition process more manageable and controllable.

Inventive Principle:

Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces contact resistance to below 1×10−9 ohm-cm2 for both p-type and n-type source/drain features, improving the efficiency of source/drain contact formation in stacked multi-gate devices.

Implementation Method 1

selectively depositing a first silicide layer on p-type source/drain features using metal precursors selective to silicon germanium surfaces

Methodology Applied

Scientific EffectSelective chemical deposition: Chemical Vapour Deposition

Implementation Method 2

using a self-assembled monolayer blocking layer on germanium-free surfaces

Methodology Applied

Scientific EffectSelf-assembly: Self-Assembly

Implementation Method 3

reduce contact resistance to below 1×10−9 ohm-cm2 for both p-type and n-type source/drain features

Methodology Applied

Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS20250031419A1Stacked Multi-Gate Device With Reduced Contact Resistance And Methods For Forming The Same

Publication Date: 2025.01.23 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Method to form low-contact-resistance contacts to source/drain features are provided. A method of the present disclosure includes receiving a workpiece including an opening that exposes a surface of an n-type source/drain feature and a surface of a p-type source/drain feature, selectively depositing a first silicide layer on the surface of the p-type source/drain feature while the surface of the n-type source/drain feature is substantially free of the first silicide layer, depositing a metal layer on the first silicide layer and the surface of the n-type source/drain feature, and depositing a second silicide layer over the metal layer. The selectively depositing includes passivating the surface of the surface of the n-type source/drain features with a self-assembly layer, selectively depositing the first silicide layer on the surface of the p-type source/drain feature, and removing the self-assembly layer.