Selective Stacked Contacts for Reliable Semiconductor Wire Bonding

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Solution Overview

Problem

Semiconductor fabrication processes face connectivity issues due to undesirable alloy formation between wire bonds and stacked conductive layers, leading to unreliable connections, particularly in automotive applications where reliability is critical.

Innovation Solution

The selective formation of a stacked conductive layer, such as an Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG) layer, is achieved by excluding its formation on specific conductive contacts, using polyimide layers to isolate and protect these contacts from the stacked layer, ensuring direct metal connections during wire bonding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a stacked conductive layer is formed on all conductive contacts, then electrical connectivity is improved, but undesirable alloy formation occurs between wire bonds and the stacked layer leading to unreliable connections

Engineering Contradiction:
Improveconnection reliabilityVSAvoidundesirable alloy formation
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent applies different treatments to different conductive contacts: some contacts receive the stacked conductive layer (Cu/Ni/Cr) while others are excluded. This local differentiation allows wire bonds to contact bare Al or Cu contacts without forming harmful alloys, while other contacts benefit from the stacked layer's electrical properties. The selective formation is achieved through masking techniques that prevent the stacked layer from depositing on specific contacts designated for wire bonding.

Inventive Principle:
Principle #3Local quality

2Object-generated harmful factors

If the stacked conductive layer is selectively formed only on specific conductive contacts, then alloy formation is prevented, but manufacturing complexity increases due to additional masking steps

Engineering Contradiction:
Improvealloy formation preventionVSAvoidmanufacturing process complexity
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The patent performs preliminary actions by forming the stacked conductive layer on all conductive contacts first, then selectively removing it from contacts that will be used for wire bonding. This reverse approach (adding then removing rather than selectively adding) simplifies the manufacturing process by using a single deposition step followed by selective removal, rather than requiring complex masking procedures during deposition.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The stacked conductive layer is temporarily formed on all contacts and then selectively removed from wire bond contacts. The removed material is discarded, while the remaining stacked layer on other contacts is retained and functional. This approach allows simple selective treatment through removal rather than through complex selective deposition masking.

Inventive Principle:
Principle #34Discarding and recovering

3Device complexity

If wire bonds are bonded directly to conductive contacts, then simple direct connection is achieved, but undesirable alloys like gold-aluminum intermetallics form causing connection failures

Engineering Contradiction:
Improveconnection structure simplicityVSAvoidwire bond reliability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent creates local quality differences by ensuring that specific conductive contacts designated for wire bonding remain as bare Al or Cu without the stacked Cu/Ni/Cr layer. This local absence of the stacked layer prevents harmful alloy formation (such as Au-Al intermetallics) while maintaining simple direct wire-to-contact bonding structure. The wire bonds achieve both simplicity and reliability by bonding directly to compatible metals.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20240128215A1Semiconductor device with stacked conductive layers and related methods
Publication Date: 2024.04.18 SEMICON COMPONENTS IND LLC
  • US20240128215A1 patent drawing
  • US20240128215A1 patent drawing
  • US20240128215A1 patent drawing

AI summary

A device may include an insulating layer disposed on a frontside of a semiconductor layer, and may include a first conductive contact disposed in a first opening in the insulating layer. The device may include a second conductive contact disposed in a second opening in the insulating layer, and may include a stacked conductive layer disposed on the first conductive contact and excluded from the second conductive contact.