Stacked Core Die Package Layout for Low-Warpage Hybrid Bonding
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Solution Overview
Problem
Manufacturing multi-chip semiconductor packages with stacked core dies thinner than 30 μm is challenging due to increased warpage and deteriorating interfacial bonding quality, leading to reduced yield.
Innovation Solution
A semiconductor package design with sequentially stacked core die blocks and gap filling portions, where the outer side surfaces of the gap filling portions are coplanar, allowing for hybrid bonding and die-to-wafer bonding methods to achieve ultra-high-level stacking with improved bonding quality and reduced thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If core dies with thickness of 30 μm or less are stacked at high level, then stacking height is improved, but warpage increases and bonding quality deteriorates
Solution Approach 1:
The patent changes the physical parameters of the core dies by controlling their thickness to 30 μm or less, and modifies the stacking configuration to achieve ultra-high-level stacking while managing warpage through parameter optimization
Solution Approach 2:
The patent segments the stacking process into multiple stages with gap filling portions inserted between core die blocks, allowing for controlled bonding at each stage rather than attempting to bond all layers simultaneously, which improves overall bonding quality
2Volume of moving object
If number of stacked core dies is increased, then stacking height is improved, but interfacial bonding quality deteriorates and yield decreases
Solution Approach 1:
The patent divides the multi-layer stacking into stages with gap filling portions between core die blocks, creating intermediate bonding surfaces that maintain quality across many layers. This segmentation allows yield to be maintained even as the total number of stacked dies increases to ultra-high levels
Solution Approach 2:
The gap filling portions act as intermediary elements between core die blocks, providing stable bonding surfaces and mechanical support that enable high-yield manufacturing of ultra-high-level stacks with 30 μm or less thick dies
Data Source
AI summary
A semiconductor package includes a buffer die, a plurality of core die blocks sequentially stacked on the buffer die, a top core die on an uppermost core die block of the plurality of core die blocks, and a molding member surrounding outer side surfaces of the plurality of core die blocks and the top core die on the buffer die. Each of the core die blocks includes a plurality of core dies sequentially stacked, and a plurality of gap filling portions surrounding outer side surfaces of at least two stages of core dies of the plurality of core dies. Outer side surfaces of the plurality of gap filling portions of each of the plurality of core die blocks are coplanar.