Vertically Stacked Non-Volatile Cross Point Memory Arrays
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Solution Overview
Problem
Current memory technologies face challenges in creating smaller and denser integrated circuits with efficient data storage and retrieval in non-volatile cross point memory cells, particularly in configuring and reading multi-resistive state materials between conductive electrodes.
Innovation Solution
The development of arrays of vertically stacked tiers of non-volatile cross point memory cells, where each memory cell comprises multi-resistive state material between word lines and bit lines, with specific circuitry for voltage potential application and current-based data retrieval, allowing for persistent resistive state changes and efficient data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are configured with multi-resistive state materials between conductive electrodes, then data storage density is improved, but device complexity increases
Solution Approach 1:
The patent transitions from planar 2D memory cell arrays to vertically stacked 3D tiers, allowing multiple memory cell layers to occupy the same footprint area. This dimensional change enables higher storage density without proportionally increasing the lateral device complexity, as the vertical stacking leverages the Z-dimension to multiply capacity.
Solution Approach 2:
The bit line select circuits and row decode select circuits are designed to universally access and control multiple memory cells across different vertical tiers through shared conductive pathways. This multi-functionality allows the same control circuitry to address cells in various tiers, reducing the need for dedicated control lines for each cell and thereby managing complexity while maintaining high density.
2Quantity of substance
If vertically stacked tiers of memory cells are implemented, then storage density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The memory array is segmented into discrete vertical tiers that can be fabricated and stacked in a modular fashion. Each tier contains complete sets of word lines, bit lines, and memory cells, allowing for standardized manufacturing units that can be replicated and assembled with controlled precision requirements at each stage rather than requiring perfect alignment across the entire structure in a single process.
Solution Approach 2:
Intermediary layers such as insulating materials and sacrificial structures are introduced between vertical tiers to facilitate precise positioning and alignment during fabrication. These intermediary elements act as spacers and alignment references that reduce the direct precision requirements between active memory cell layers, enabling vertical stacking with manageable tolerances.
3Quantity of substance
If multi-resistive state materials are used for data storage, then storage capacity is improved, but reliability of state switching becomes more challenging
Solution Approach 1:
The patent employs parameter changes in the form of applied voltage potentials to reliably switch multi-resistive state materials between different resistance states. By controlling the magnitude, polarity, and duration of voltage pulses applied through word lines and bit lines, the system can deterministically transition memory cells between multiple stable resistive states, ensuring reliable data writing and reading operations despite the complexity of multi-state materials.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient data storage and retrieval in a compact, dense format by utilizing vertically stacked tiers with multi-resistive state materials and advanced circuitry, enhancing the persistence and readability of resistive states in memory cells.
Implementation Method 1
the collective material received between the two electrodes is selected or designed to be configured in a selected one of at least two different resistive states to enable storing of information by an individual memory cell
Implementation Method 2
a sense amplifier is coupled to the memory array to sense an amount of current flowing along a conductive path defined by the selected word line and the selected bit line
Data Source
AI summary
An array of vertically stacked tiers of non-volatile cross point memory cells includes a plurality of horizontally oriented word lines within individual tiers of memory cells. A plurality of horizontally oriented global bit lines having local vertical bit line extensions extend through multiple of the tiers. Individual of the memory cells comprise multi-resistive state material received between one of the horizontally oriented word lines and one of the local vertical bit line extensions where such cross, with such ones comprising opposing conductive electrodes of individual memory cells where such cross. A plurality of bit line select circuits individually electrically and physically connects to individual of the local vertical bit line extensions and are configured to supply a voltage potential to an individual of the global horizontal bit lines. Other embodiments and aspects are disclosed.