SiP Stacked Clocking Crystal Vertical Integration
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Solution Overview
Problem
Traditional multi-chip modules (MCMs) with horizontal form factors face challenges in reducing footprint and minimizing parasitic capacitance, which hinders the development of smaller wireless devices with greater functionality due to the large size of system-on-a-chip (SoC) and crystal components, as well as long crystal routing paths.
Innovation Solution
The implementation of a system-in-a-package (SiP) with vertical integration of components, such as stacking the SoC, crystal, and front-end integrated circuit (FEIC) on a substrate, reducing the footprint and parasitic capacitance by shortening crystal traces and minimizing coupling between sensitive paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional multi-chip modules (MCMs) with horizontal form factor are used, then radio frequency functionality is provided, but the package footprint becomes large due to the size of SoC and crystal components
Solution Approach 1:
The patent transitions from a horizontal two-dimensional layout to a vertical three-dimensional stacked configuration. The crystal is positioned above the SoC in the vertical dimension, allowing both components to coexist in a compact footprint while maintaining their functional requirements. This dimensional change resolves the contradiction by eliminating the need for large horizontal spacing between components.
Solution Approach 2:
The patent implements a nested arrangement where the crystal is effectively positioned within the vertical projection of the SoC footprint. The crystal trace routes from the crystal down through the substrate to the SoC, creating a nested spatial relationship that minimizes the overall package area while keeping both components accessible and functional.
2Reliability
If long crystal routing paths are used in traditional MCM designs, then crystal connectivity is achieved, but parasitic capacitance increases adversely affecting oscillation startup
Solution Approach 1:
The patent utilizes the vertical dimension for crystal trace routing instead of confining traces to the horizontal substrate plane. By routing the crystal trace vertically through the substrate from the crystal above to the SoC below, the path length is significantly reduced compared to horizontal routing alternatives, thereby minimizing parasitic capacitance and improving oscillation startup reliability.
3Object-affected harmful factors
If horizontal component arrangement is used in MCM, then radio frequency functionality is integrated, but signal coupling between crystal routing traces and other sensitive paths increases
Solution Approach 1:
The patent employs vertical routing for the crystal trace through the substrate, which spatially separates it from other horizontal routing traces on the substrate. This three-dimensional routing strategy reduces electromagnetic coupling and interference between the crystal trace and other sensitive signal paths, as the vertical trajectory minimizes parallel trace interactions that cause signal coupling.
Solution Approach 2:
The patent implements localized trace routing where the crystal trace is confined to a specific vertical path through the substrate rather than spreading horizontally. This concentrated routing approach minimizes the trace's exposure to other signal paths and reduces the overall routing complexity, while still achieving connectivity to the SoC.
Data Source
AI summary
A packaged module for use in a wireless communication device has a substrate supporting a crystal and a first die that includes at least a microprocessor and one or more of radio frequency transmitter circuitry and radio frequency receiver circuitry. The first die is disposed between the crystal and the substrate. An overmold encloses the first die and the crystal. The substrate also supports a second die that includes at least a power amplifier for amplifying a radio frequency input signal, where the second die is disposed on an opposite side of the substrate from the first die and the crystal.