Stacked Deck Interconnect Layout for Dense Memory Routing
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Solution Overview
Problem
As the number of components in an integrated circuit die increases, optimizing spacing and connectivity between microelectronic device components and peripheral circuits becomes challenging, particularly in achieving high density logic and memory applications.
Innovation Solution
The development of a microelectronic device with stacked interconnect structures, comprising alternating tiers of conductive and insulative materials, where interconnect structures are formed from the conductive material of the tiers, enabling vertical stacks of interconnects separated by insulative material, and allowing data lines from one deck to be electrically coupled to interconnect structures of another deck vertically offset.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of components in an integrated circuit die is increased to enable high density logic and memory applications, then the device functionality and capacity are improved, but optimizing spacing and connectivity between microelectronic device components and peripheral circuits becomes more challenging
Solution Approach 1:
The patent transitions from planar interconnect arrangements to three-dimensional stacked interconnect structures. Multiple interconnect layers are vertically stacked and offset from one another, enabling components to be connected through vertical pathways rather than only lateral routing. This dimensional change allows increased component density while maintaining manageable spacing and connectivity, as vertical stacking provides additional routing dimensions that simplify the optimization of signal paths between components and peripheral circuits.
2Quantity of substance
If stacked interconnect structures are implemented to increase interconnect density, then the density of microelectronic device components is improved, but the structural complexity of the interconnect architecture increases
Solution Approach 1:
The interconnect architecture is segmented into multiple discrete stacked layers, each serving specific routing functions. The offset arrangement divides the interconnect space into distinct vertical levels, allowing independent design and optimization of each layer. This segmentation manages architectural complexity by breaking down the overall interconnect system into modular units that can be designed, fabricated, and analyzed separately, while still achieving high overall density through their combined vertical stacking.
Data Source
AI summary
A microelectronic device includes a first deck, a second deck, and a first conductive structure. The first deck has one or more memory cell strings and a stack of data lines operably connected to the one or more memory cell strings. Each of the one or more memory cell strings includes a first conductive contact. The second deck is vertically adjacent to the first deck and includes stacked tiers of conductive material defining a first interconnect structure. The first interconnect structure is operably connected to a data line of the stack of data lines. The first conductive structure is electrically coupled to the first conductive contact of the first deck and to the first interconnect structure of the second deck. Methods of forming the microelectronic device are also disclosed, as are memory devices, electronic signal processor devices, and electronic systems comprising such microelectronic devices.