Stacked Decoupling Capacitor Assemblies for Low Parasitic Inductance
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Solution Overview
Problem
Increased parasitic inductances in semiconductor chips due to higher switching speeds necessitate improved microelectronic assemblies with enhanced decoupling capacitors to maintain voltage stability and supply current effectively.
Innovation Solution
A decoupling capacitor structure comprising alternating dielectric layers and internal electrode layers, with external terminals connected to interposers, is integrated into a microelectronic assembly to improve power delivery and reduce parasitic inductances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If switching speeds in semiconductor chips are increased, then productivity is improved, but parasitic inductances increase causing voltage instability
Solution Approach 1:
The patent transitions from planar capacitor configurations to three-dimensional stacked capacitor structures. Multiple capacitor layers are vertically stacked on the interposer, utilizing the vertical dimension to increase capacitance density without expanding the horizontal footprint. This dimensional change allows sufficient decoupling capacitance to be provided even at high switching speeds where parasitic inductance is a concern.
Solution Approach 2:
The patent implements nested capacitor structures where smaller capacitors are placed within or between larger capacitor layers. Multiple capacitor elements are nested vertically and horizontally within the interposer structure, maximizing the use of available space. This nesting approach increases the total decoupling capacitance available to counteract parasitic inductance effects at high switching frequencies.
2Reliability
If decoupling capacitance is increased to maintain voltage stability, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple capacitor layers, interconnect layers, and interposer structures into a single integrated assembly. The decoupling capacitors are manufactured and assembled as an integrated unit with the interposer, rather than as separate components. This merging reduces the overall system complexity while providing the necessary decoupling capacitance for voltage stability at high switching speeds.
Solution Approach 2:
The interposer structure serves multiple functions: it provides mechanical support, electrical interconnection, and hosts the decoupling capacitors. The same interposer that facilitates chip-to-board connectivity also integrates the capacitor array, eliminating the need for separate capacitor components and reducing overall device complexity while maintaining voltage stability.
3Reliability
If capacitor size is increased to reduce parasitic inductance, then reliability is improved, but area occupied increases
Solution Approach 1:
The patent utilizes vertical stacking to increase capacitor capacity without expanding horizontal footprint. Multiple capacitor layers are stacked in the Z-direction, allowing the equivalent of a large-area capacitor to be achieved within a small footprint by exploiting the third dimension. This reduces the area occupied on the interposer while providing sufficient capacitance to counteract parasitic inductance.
Solution Approach 2:
The patent employs composite capacitor structures with multiple dielectric layers and electrode configurations. By using composite material stacks with high dielectric constants and optimized conductor patterns, the effective capacitance is increased without proportionally increasing the physical footprint. This allows reduced parasitic inductance to be achieved within constrained area budgets on the interposer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively addresses the issue of voltage stability and current supply by reducing parasitic inductances, enhancing the performance of microelectronic assemblies and supporting higher switching speeds in semiconductor chips.
Implementation Method 1
one or more decoupling capacitors are also typically employed so that any sudden requirement for current can be supplied to the chip with the voltage maintained constant or nearly constant
Implementation Method 2
The decoupling capacitor contains alternating dielectric layers and internal electrode layers
Data Source
AI summary
Decoupling capacitor structures, sacrificial component structures, and assemblies are provided. For example, a decoupling capacitor structure includes a first interposer having opposing first and second surfaces and a decoupling capacitor having opposing first and second surfaces. The decoupling capacitor is disposed adjacent the first interposer such that the first surface of the decoupling capacitor is adjacent the second surface of the first interposer. A first external terminal and a third external terminal of the decoupling capacitor are formed on the first surface of the decoupling capacitor and are electrically connected to the first interposer. The decoupling capacitor structure may include a second interposer such that the decoupling capacitor is sandwiched between the first and second interposers. One or more decoupling capacitor structures may be disposed in a substrate to form a decoupling capacitor assembly, and multiple decoupling capacitor structures may be stacked to form a multilayer structure.