Stacked-Gate Delay Cells in Ring Oscillators for Phase Noise

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Solution Overview

Problem

Existing clock source generators, such as those using ring-oscillators or phase-locked loops, suffer from device noise issues that limit their phase noise performance.

Innovation Solution

The implementation of stacked gate delay cells and pseudo-load transistors in ring oscillators, which increase the effective channel area of transistors and supply more drain current to delay cells, reducing phase noise without the need for costly inductors or complex filters.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If inductor-capacitor tank (LC-tank) ring oscillators are used to reduce noise, then phase noise performance is improved, but device area increases and sensitivity to process variations increases

Engineering Contradiction:
Improvephase noise performanceVSAvoidsemiconductor die area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent extracts and removes the inductor component from the traditional LC-tank ring oscillator design. By eliminating the inductor, the circuit achieves reduced phase noise performance without requiring large semiconductor die area, thus resolving the contradiction between noise reduction and area consumption.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces expensive and area-consuming inductor components with simpler, more integrated transistor-based delay cell structures. This substitution uses standard semiconductor fabrication processes to achieve noise reduction without the need for large external inductors or complex passive components.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

2Reliability

If additional phase noise filter circuits are provided to reduce noise, then phase noise performance is improved, but device complexity increases

Engineering Contradiction:
Improvephase noise performanceVSAvoidcircuit structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the phase noise filtering function directly into the delay cell structure itself. By integrating noise reduction capabilities within the existing delay cells rather than adding separate filter circuits, the design achieves improved phase noise performance without increasing overall device complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The delay cells in the patent serve multiple functions simultaneously: they provide the necessary signal delay for oscillation while also functioning as phase noise filtering elements. This multi-functionality eliminates the need for dedicated filter circuits, thereby maintaining device simplicity while improving noise performance.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If transistor channel area is increased to reduce noise, then phase noise performance is improved, but device area increases

Engineering Contradiction:
Improvephase noise performanceVSAvoidsemiconductor die area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent applies local quality by concentrating increased transistor channel area specifically within the delay cell structures where it is most needed for noise reduction. Rather than uniformly increasing area across the entire circuit, the design strategically places larger channel area transistors in critical delay cells, achieving noise reduction with minimal overall area increase.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12244312B2Low noise ring oscillator devices and methods
Publication Date: 2025.03.04 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12244312B2 patent drawing
  • US12244312B2 patent drawing
  • US12244312B2 patent drawing

AI summary

A device including delay cells connected in series and in a feedback loop to provide a ring oscillator. At least one of the delay cells in the ring oscillator is a stacked gate delay cell that includes two or more PMOS transistors having first drain/source paths connected in series to each other and having first gates connected to each other and two or more NMOS transistors having second drain/source paths connected in series to each other and to the first drain/source paths and having second gates connected to each other and to the first gates.