Monolithic Stacked Devices With Multiple Gate Dielectrics
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Solution Overview
Problem
Conventional semiconductor technologies face challenges in achieving reliable high-performance computing for server applications due to differing reliability and performance needs across various devices, such as logic and I/O devices, which require specific gate dielectrics, leading to inefficiencies and increased development costs.
Innovation Solution
A semiconductor structure with stacked devices featuring different gate dielectrics, including interfacial and high-k gate dielectric layers of varying thicknesses and compositions, optimized for each device type to enhance performance and reliability, allowing for monolithic device stacking and improved breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single gate dielectric structure is used for all devices, then manufacturing complexity is reduced, but device performance and reliability cannot be optimized for different device types
Solution Approach 1:
The semiconductor structure is divided into multiple device regions (first device region with logic devices, second device region with I/O devices), where each region has its own tailored gate dielectric structure. This segmentation allows each device type to have optimized gate dielectrics while maintaining overall system integration.
Solution Approach 2:
Different gate dielectric structures are implemented in different device regions according to specific performance requirements. Logic devices receive one gate dielectric configuration while I/O devices receive another, allowing local optimization of device reliability and performance without requiring a completely separate manufacturing process.
2Reliability
If different gate dielectrics are used for logic and I/O devices, then device performance is optimized, but manufacturing process complexity increases
Solution Approach 1:
The manufacturing process is segmented into region-specific steps where first device regions and second device regions receive different gate dielectric treatments. This allows performance optimization for logic and I/O devices while organizing the manufacturing process into manageable, region-based operations.
Solution Approach 2:
The gate dielectric parameters (thickness, material composition) are changed according to device region requirements. Logic devices receive gate dielectrics with specific thickness and material properties, while I/O devices receive different parameters, allowing performance optimization through parameter tuning rather than completely different manufacturing approaches.
3Reliability
If gate dielectric thickness is increased, then breakdown voltage is improved, but device performance for logic operations may be compromised
Solution Approach 1:
Gate dielectric thickness is locally optimized for different device types. I/O devices receive thicker gate dielectrics for high breakdown voltage requirements, while logic devices receive thinner gate dielectrics for optimal switching performance, allowing each device type to operate at its performance peak without compromising the other.
Solution Approach 2:
The gate dielectric thickness parameter is varied according to device function. By changing this critical parameter between device regions, the patent achieves both high breakdown voltage where needed and optimal logic performance where required, resolving the trade-off between reliability and productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach optimizes device performance and reliability by tailoring gate stack dielectrics for specific device functionalities, addressing the limitations of conventional technologies and reducing development costs by enabling efficient monolithic stacking and improved circuit performance.
Implementation Method 1
The different gate dielectrics include interfacial dielectric layers and high-k gate dielectric layers. Throughout this application, the term 'high-k' denotes a material having a dielectric constant, as measured in vacuum, of greater than 4.0.
Data Source
AI summary
A semiconductor structure including a plurality of stacked devices having different gate dielectrics is provided. The different gate dielectrics for the stacked devices are designed to improve the performance and the reliability for each of the stacked devices.