3D Stacked Integrated Circuit Dice for Distributed Computing
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Solution Overview
Problem
The von Neumann bottleneck, which arises from the separation of processors and memory in computer architectures, limits processing speed due to lower data bus throughput compared to processor speed, and this issue is exacerbated in distributed computing environments where multiple processors experience compounded delays.
Innovation Solution
The implementation of a distributed computing system with integrated circuit dice arranged in layers, where each die has multiple connection pads for direct communication, and a connector system that allows for dynamic reconfiguration and communication between adjacent dice, enabling efficient data transfer and processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If processors and memory are separated on a motherboard, then device complexity is reduced and ease of manufacture is improved, but processing speed deteriorates due to the von Neumann bottleneck
Solution Approach 1:
The system is divided into multiple independent processing nodes, each containing a processor and memory unit. These nodes are distributed across multiple layers rather than being consolidated on a single motherboard, allowing parallel processing while maintaining manufacturing simplicity for each individual node.
Solution Approach 2:
The architecture transitions from a two-dimensional motherboard layout to a three-dimensional stacked configuration with multiple layers. This vertical arrangement reduces the von Neumann bottleneck by providing direct access paths between processors and memory across layers, eliminating the need for long horizontal data bus traversals.
2Device complexity
If multiple motherboards are connected within one cabinet to reduce overhead, then device complexity is reduced, but processing speed deteriorates due to compounded delays on data buses
Solution Approach 1:
Multiple processing nodes are merged into a single integrated circuit package with multiple layers. This consolidation eliminates the need for external motherboard connections and data bus traversals between separate boards, reducing communication overhead and delay while maintaining manageable device complexity through modular integration.
Solution Approach 2:
The patent introduces on-chip interconnect structures and crossbar switches as intermediaries between processing units and memory across different layers. These intermediaries provide direct, high-speed communication paths that eliminate the need for external motherboard data buses, reducing communication delay while maintaining system modularity.
3Speed
If processor speed increases faster than memory throughput, then processing capability is improved, but the von Neumann bottleneck worsens causing processor under-utilization
Solution Approach 1:
Each processing node is equipped with locally integrated memory units directly connected to the processor within the same integrated circuit package. This local memory architecture eliminates the need for processors to wait for data transfer over external buses, allowing processors to operate at full speed while maintaining balanced memory throughput capability.
Data Source
AI summary
On a typical motherboard the processor and memory are separated by a printed circuit data bus that traverses the motherboard. Throughput, or data transfer rate, on the data bus is much lower than the rate at which a modern processor can operate. The difference between the data bus throughput and the processor speed significantly limits the effective processing speed of the computer when the processor is required to process large amounts of data stored in the memory. The processor is forced to wait for data to be transferred to or from the memory, leaving the processor under-utilized. The delays are compounded in a distributed computing system including a number of computers operating in parallel. The present disclosure describes systems, method and apparatus that tend to alleviate delays so that memory access bottlenecks are not compounded within distributed computing systems.