Stacked Die Package Alignment Using Embedded Bonding Marks

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Solution Overview

Problem

Integration of multiple semiconductor devices in wafer level packaging poses challenges, particularly in achieving precise alignment and efficient electrical connections between dies.

Innovation Solution

A method involving fusion bonding of dies to a carrier substrate, followed by sequential deposition of dielectric and bonding layers, and hybrid bonding of additional dies to form a reconstructed wafer with improved alignment and electrical connectivity through bonding vias and pads.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple semiconductor devices are integrated at wafer level, then productivity and integration density are improved, but manufacturing precision and alignment difficulty worsen

Engineering Contradiction:
Improveintegration densityVSAvoidalignment precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The wafer is divided into multiple individual dies that can be processed and packaged separately yet remain on the wafer substrate. This segmentation allows each die to be handled independently for precise alignment while maintaining overall wafer-level integration, resolving the contradiction between high integration density and alignment precision.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A carrier substrate is introduced as an intermediary between the dies and the final package. The carrier substrate provides a stable platform for wafer-level processing and enables precise positioning of multiple dies during bonding operations, thereby achieving both high integration and manufacturing precision.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If wafer level packaging is used, then productivity is improved, but device complexity increases

Engineering Contradiction:
Improvepackaging efficiencyVSAvoidprocess complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Multiple packaging operations are merged into a single wafer-level process. Instead of packaging each die individually, the method combines die attachment, bonding layer formation, and electrical connection establishment into integrated wafer-level steps, thereby improving productivity while managing process complexity through consolidation.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The wafer-level packaging process serves multiple functions simultaneously: it performs die attachment, forms bonding layers, creates electrical connections, and enables subsequent die stacking. This multi-functionality improves packaging efficiency while the standardized universal process reduces overall complexity compared to multiple separate operations.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Manufacturing precision

If precise alignment is achieved between dies, then manufacturing precision is improved, but loss of time increases

Engineering Contradiction:
Improvealignment precisionVSAvoidalignment time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

Alignment marks are pre-formed on the carrier substrate and dies before the bonding process. This preliminary action enables rapid automated alignment during packaging without requiring time-consuming manual adjustment, thereby achieving high alignment precision while minimizing the time lost during the alignment process.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enhances yield and reduces costs by ensuring high precision alignment and efficient electrical connections, facilitating the integration of known good dies in a reconstructed wafer.

Implementation Method 1

The first bonding layer is fusion bonded to the carrier substrate

Methodology Applied
Scientific EffectFusion bonding: Welding

Implementation Method 2

The third bonding layer is hybrid bonded to the second bonding layer of the first die

Methodology Applied
Scientific EffectHybrid bonding: Welding

Data Source

PatentUS20250336892A1package
Publication Date: 2025.10.30 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250336892A1 patent drawing
  • US20250336892A1 patent drawing
  • US20250336892A1 patent drawing

AI summary

A package includes a carrier substrate, a first die, and a second die. The first die and the second die are stacked on the carrier substrate in sequential order. The first die includes a first bonding layer, a second bonding layer, and an alignment mark embedded in the first bonding layer. The second die includes a third bonding layer. A surface of the first bonding layer form a rear surface of the first die and a surface of the second bonding layer form an active surface of the first die. The rear surface of the first die is in physical contact with the carrier substrate. The active surface of the first die is in physical contact with the third bonding layer of the second die.