Stacked Semiconductor Die Assembly Without TSVs or Bumping
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Solution Overview
Problem
The challenge in semiconductor die assemblies is to reduce the size and cost of stacked semiconductor packages while maintaining signal integrity, as traditional methods like through-substrate vias (TSVs) and bumping processes are costly and prone to yield and reliability issues.
Innovation Solution
The approach involves flipping the master die to face the substrate with conductive pillars for direct chip attachment, eliminating the need for TSVs and the bumping process, and using bonding wires through substrate openings to connect the master and slave dies to substrate bond pads, establishing electrical connections via conductive traces in the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-substrate vias (TSVs) and bumping processes are used to stack semiconductor dies, then electrical connections between dies are established, but manufacturing cost increases and yield/reliability issues arise
Solution Approach 1:
The patent extracts and eliminates the TSV and bumping process from the semiconductor die stacking methodology. Instead of using complex TSV structures that require costly manufacturing processes, the invention uses direct wire bonding through substrate openings to establish electrical connections, thereby removing the source of yield and reliability issues associated with TSVs while reducing manufacturing cost
Solution Approach 2:
The patent replaces expensive TSV structures with simpler, more cost-effective wire bonding technology. The wire bonding method uses inexpensive materials and processes compared to TSV fabrication, achieving the same electrical connection function at lower cost without the reliability penalties of the disposable TSV approach
2Reliability
If TSVs and bumping processes are used for die stacking, then electrical connections are achieved, but device complexity increases
Solution Approach 1:
The patent removes the complex TSV and bumping process steps from the manufacturing flow. By extracting these complex processes and replacing them with direct wire bonding through substrate openings, the invention maintains signal integrity while dramatically reducing device complexity and the number of manufacturing steps required
Solution Approach 2:
Instead of building complex three-dimensional TSV structures from the substrate up, the patent inverts the approach by using conventional wire bonding technology in a straightforward manner through substrate openings, achieving the same electrical interconnection function with simpler, more direct processes
3Area of stationary object
If stacked semiconductor dies are used to reduce package footprint, then space constraints are addressed, but manufacturing cost increases due to TSVs and bumping
Solution Approach 1:
The patent merges the die stacking function with conventional wire bonding technology. By combining the vertical stacking approach with the simpler wire bonding process (rather than using separate TSV and bumping processes), the invention achieves footprint reduction while avoiding the cost penalties of complex manufacturing
Solution Approach 2:
The patent replaces expensive TSV structures with inexpensive wire bonding technology, achieving the same space-saving stacked package configuration at lower manufacturing cost. The wire bonding approach uses cheaper materials and processes while maintaining the compact vertical architecture
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method provides a lower-cost alternative for semiconductor die assemblies with maintained signal integrity, comparable to traditional methods, and reduces the footprint of the stack without the costs associated with TSVs and bumping processes.
Implementation Method 1
conductive pillars for direct chip attachment, eliminating the need for TSVs and the bumping process
Implementation Method 2
using bonding wires through substrate openings to connect the master and slave dies to substrate bond pads
Data Source
AI summary
Stacked semiconductor dies for semiconductor device assemblies and associated methods and systems are disclosed. In some embodiments, the semiconductor die assembly includes a substrate with a first opening in an inner portion and a second opening in an outer portion of the substrate. Further, the semiconductor die assembly can include a master die attached to a front side of the substrate, where the master die includes a first bond pad proximate to the first opening and a second bond pad proximate to the second opening. The first and second bond pads of the master die can be coupled with first and second substrate bond pads on a back side of the substrate, opposite to the front side, using first and second bonding wires extending through the first and second openings, respectively.