Stacked Die Package Architecture With Base-Die Power Routing
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Solution Overview
Problem
Current packaging architectures for integrated circuits (ICs) are limited in their ability to scale to higher bandwidth and signal speeds required for next-generation servers, due to issues like bandwidth reduction, signal delay, signal loss, and signal distortion.
Innovation Solution
The proposed solution involves vertically stacking IC dies and electrically coupling them at a lateral edge to a base IC die, using interconnects that include oxide-oxide bonds and metal-metal bonds, allowing for improved power delivery and signal speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional packaging architectures are used, then manufacturing simplicity is maintained, but bandwidth and signal speed are limited
Solution Approach 1:
The patent transitions from conventional two-dimensional planar packaging to three-dimensional vertical stacking, where multiple IC dies are stacked vertically and coupled at lateral edges. This dimensional change enables shorter signal paths and higher bandwidth while maintaining manufacturing feasibility through established bonding techniques.
Solution Approach 2:
The patent divides the system into multiple separate IC dies that are vertically stacked and laterally coupled, rather than using a single large die. This segmentation allows for modular design, improved signal integrity, and the ability to use standard manufacturing processes for each die while achieving superior overall performance.
2Power
If vertically stacked IC dies are used, then power delivery and signal speed are improved, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary vertical stacking and bonding of IC dies before final package assembly. By pre-assembling the vertical stack with lateral edge couplings in advance, the manufacturing process is simplified in the final assembly stage, and power delivery pathways are optimized through the vertical configuration.
3Reliability
If lateral edge coupling is used, then signal loss and distortion are reduced, but interconnect complexity increases
Solution Approach 1:
The patent uses lateral edge coupling as an intermediary mechanism between vertically stacked IC dies. This coupling method provides direct electrical pathways that reduce signal loss and distortion compared to traditional vertical interconnects, while the coupling structure itself manages the complexity of interconnections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances power delivery and signal speed while reducing the complexity of the package, enabling better performance in high-bandwidth applications such as next-generation servers.
Implementation Method 1
electrically coupling them at a lateral edge to a base IC die, using interconnects that include oxide-oxide bonds and metal-metal bonds
Data Source
AI summary
Embodiments of a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including conductive traces that are parallel to the first and second surfaces and exposed at the third surface; a second IC die having a fourth surface and including voltage regulator circuitry; and a third IC die having a fifth surface, wherein the third surface of the first IC die is electrically coupled to the fifth surface of the third IC die by first interconnects, the fourth surface of the second IC die is electrically coupled to the fifth surface of the third IC die by second interconnects, and the first IC die is electrically coupled to the second IC die by conductive pathways in the third IC die.