Stacked Semiconductor Die Bump Formation for Reduced Package Height
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Solution Overview
Problem
Conventional semiconductor package-on-package (PoP) designs are prone to increased height, are time-consuming and costly to manufacture, and prone to defects due to individual stacking of semiconductor die.
Innovation Solution
A method involving the direct formation of bumps on a conductive layer between stacked semiconductor die, eliminating the need for a substrate and simplifying the stacking process by using a carrier to mount and singulate wafers, then depositing an encapsulant and forming interconnect structures directly on the lower die.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional PoP designs use substrate mounting for individual stacking of semiconductor die, then electrical connectivity is achieved, but package height increases and manufacturing becomes time-consuming and costly
Solution Approach 1:
The patent merges the substrate mounting function with the semiconductor die stacking process by forming bumps directly on the lower die's conductive layer. This eliminates the separate substrate mounting step, reducing package height while maintaining manufacturing efficiency through direct wafer-to-wafer bonding.
Solution Approach 2:
The patent extracts and eliminates the substrate from the conventional PoP structure. By forming bumps directly on the lower die without requiring substrate mounting, the design removes an unnecessary component that increases height and complexity, achieving a more compact and efficient structure.
2Ease of manufacture
If individual stacking of semiconductor die is performed on substrate, then electrical connections are established, but manufacturing complexity and defect risk increase
Solution Approach 1:
The patent applies preliminary action by forming the bump structures on the conductive layer of the lower die before the stacking process. This pre-formed bump structure eliminates the need for complex post-stack alignment and bonding operations, simplifying manufacturing and reducing defect risks associated with individual die stacking.
3Device complexity
If bumps are formed on conductive layer between stacked die, then manufacturing process is simplified, but precise alignment and formation control are required
Solution Approach 1:
The patent applies self-service through self-aligned bump formation processes where the bump structures are formed directly on the conductive layer in a controlled sequence. The conductive layer pattern and wafer alignment mechanisms provide inherent guidance for bump placement, reducing the need for external alignment fixtures and simplifying the overall process while maintaining high precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the package height, simplifies the manufacturing process, and decreases the likelihood of defects by enabling cost-effective vertical stacking of semiconductor die with improved thermal characteristics and electrical connectivity.
Implementation Method 1
depositing an encapsulant over the stacked first and second semiconductor die
Data Source
AI summary
A semiconductor device has a first semiconductor wafer mounted to a carrier. A second semiconductor wafer is mounted to the first semiconductor wafer. The first and second semiconductor wafers are singulated to separate stacked first and second semiconductor die. A peripheral region between the stacked semiconductor die is expanded. A conductive layer is formed over the carrier between the stacked semiconductor die. Alternatively, a conductive via is formed partially through the carrier. A bond wire is formed between contact pads on the second semiconductor die and the conductive layer or conductive via. An encapsulant is deposited over the stacked semiconductor die, bond wire, and carrier. The carrier is removed to expose the conductive layer or conductive via and contact pads on the first semiconductor die. Bumps are formed directly on the conductive layer and contact pads on the first semiconductor die.