Stacked Die Cavity Package for Compact PoP Integration
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Solution Overview
Problem
As computing devices increase in performance and shrink in size, package-on-package architectures face challenges in space utilization due to the need for substrates to accommodate devices, interconnects, and vias, leading to form factor growth and pin reduction issues.
Innovation Solution
The development of stacked die cavity packages that enable traditional top side ball attach, mold, and through-mold interconnect (TMI) drilling with large dies and die stacks, using a cavity substrate with multiple layers of dielectric material interspersed with conductive material, mold compound for stability and insulation, and through-mold vias for efficient communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If package-on-package architectures are used to increase performance, then device capabilities are improved, but substrate space utilization deteriorates due to requirements for devices, interconnects, and vias
Solution Approach 1:
The patent transitions from planar substrate routing to three-dimensional vertical stacking by forming cavities through the substrate and placing dies above and below the substrate plane. This dimensional change allows interconnects to route vertically through the substrate thickness rather than consuming lateral substrate area, enabling higher device capability density within the same footprint.
Solution Approach 2:
The patent implements nested structures by placing first dies above the substrate and second dies below the substrate, with both dies connected through cavities formed in the substrate. The substrate acts as a central hub nesting multiple dies in different spatial zones, maximizing space utilization while maintaining electrical connectivity.
2Adaptability or versatility
If substrates accommodate devices and interconnects, then communication functionality is improved, but form factor growth occurs
Solution Approach 1:
The patent utilizes the substrate thickness dimension by forming cavities that extend through the substrate and positioning dies at different depths above and below the substrate. This vertical arrangement enables communication functionality between multiple dies without increasing the lateral form factor, as all components are contained within the same footprint envelope.
Solution Approach 2:
The patent employs a mold compound as a protective shell that encapsulates the dies and fills the cavities, providing mechanical support and environmental protection. This thin-film encapsulation allows the package to maintain a compact form factor while accommodating the three-dimensional die stack configuration.
3Adaptability or versatility
If PoP architectures are implemented, then device integration is improved, but pin requirements increase
Solution Approach 1:
The patent extracts the interconnect function from traditional substrate trace routing and implements it through direct mechanical and electrical coupling of dies to the substrate contact pads. By taking out the intermediate routing layer and using through-substrate vias and direct die-to-substrate bonding, the design reduces the number of required pins while maintaining integration functionality.
Solution Approach 2:
The patent merges multiple functions into the substrate structure: the substrate serves as both the mechanical support platform and the electrical interconnect medium through its contact pads and through-substrate vias. This consolidation of support and interconnect functions into a single substrate structure reduces the overall pin count required compared to separate interconnect layers.
Data Source
AI summary
An apparatus is provided which comprises: a plurality of dielectric layers forming a substrate, a plurality of first conductive contacts on a first surface of the substrate, a cavity in the first surface of the substrate defining a second surface parallel to the first surface, a plurality of second conductive contacts on the second surface of the substrate, one or more integrated circuit die(s) coupled with the second conductive contacts, and mold material at least partially covering the one or more integrated circuit die(s) and the first conductive contacts. Other embodiments are also disclosed and claimed.