Stacked Memory Die Identifier Circuits for Conflict-Free Chip IDs
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Solution Overview
Problem
Conflicts arise during the manufacturing of three-dimensional memory stacks due to identical chip identifiers assigned before stacking, leading to issues with memory chips in the stack.
Innovation Solution
A method for automatically generating chip identifiers in a stacked structure using identifier generation circuits, where each semiconductor die generates a unique identifier based on the previous die's identifier, through electrical connections and bit-shifting operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If chip identifiers are set before stacking, then manufacturing process is simplified, but identifier conflicts occur between different memory chips in the stack
Solution Approach 1:
The patent applies preliminary action by pre-configuring identifier generation circuits in each semiconductor die that can automatically generate unique identifiers after stacking. The circuits are prepared in advance with the capability to receive signals from adjacent dies and generate unique identifiers through bit-shifting operations, resolving the conflict between early identifier assignment and uniqueness reliability.
Solution Approach 2:
The identifier generation circuits implement self-service by automatically generating unique identifiers for each die based on signals from neighboring dies. Each circuit independently produces its identifier through bit-shifting operations without requiring external intervention, ensuring uniqueness while maintaining manufacturing simplicity.
2Reliability
If identifiers are generated after stacking, then identifier uniqueness is ensured, but manufacturing complexity increases
Solution Approach 1:
The patent replaces complex mechanical or manual identifier assignment processes with electronic identifier generation circuits. These circuits use electrical signals and bit-shifting operations to automatically generate unique identifiers, significantly reducing manufacturing complexity while ensuring identifier uniqueness through the electrical connection between stacked dies.
3Measurement precision
If manual identifier assignment is used, then identifier correctness can be verified, but production efficiency decreases
Solution Approach 1:
The patent implements feedback through electrical connections between identifier generation circuits of adjacent dies. Each circuit receives a signal from a neighboring die and uses it as input for generating its own identifier through bit-shifting operations. This feedback mechanism ensures identifier correctness while enabling automatic generation that maintains high production efficiency.
Data Source
AI summary
A method for automatically generating chip identifier for semiconductor dies in a stacked structure is provided. The method includes the following steps: obtaining a first semiconductor die and a second semiconductor die, wherein the first semiconductor die and the second semiconductor die include a first identifier generation circuit and a second identifier generation circuit, respectively; forming a stacked structure by stacking the second semiconductor die on the first semiconductor die, wherein the first identifier generation circuit is electrically connected to the second identifier generation circuit; and generating a first chip identifier and a second chip identifier for the first semiconductor die and the second semiconductor die by the first identifier generation circuit and the second identifier generation circuit, respectively. The second chip identifier is a bit-shifted value of the first chip identifier.