Stacked Semiconductor Die Configuration for Circuit Density

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Solution Overview

Problem

The increasing complexity and density of electronic circuits require innovative packaging solutions to enhance device integration, functionality, and reduce size, while existing technologies face challenges in efficiently stacking devices with different functionalities and technologies.

Innovation Solution

The proposed solution involves a substrate with a cavity for one semiconductor die and another die stacked above it, with mechanical and electrical bonding using coupling mechanisms like solder balls or micro bumps, allowing for flexible integration of various types and sizes of dies, including FPGA circuitry, to form a stacked configuration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If devices are arranged in a three-dimensional stacked configuration, then circuit density and device integration are increased, but device complexity and manufacturing difficulty increase

Engineering Contradiction:
Improvecircuit densityVSAvoiddevice complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent divides the electronic system into multiple separate semiconductor dies that are stacked vertically. Each die can be independently fabricated, tested, and packaged, then bonded together to form a three-dimensional assembly. This segmentation allows complex functionality to be distributed across multiple simpler components, increasing overall circuit density while managing device complexity through modular architecture.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from traditional two-dimensional planar arrangement of electronic components to a three-dimensional stacked configuration. By adding the vertical dimension, the system achieves higher circuit density without increasing the footprint area. Multiple dies are bonded face-to-face in the vertical direction, creating a stacked architecture that充分利用s three-dimensional space for enhanced integration.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Speed

If devices are stacked in a three-dimensional configuration, then interconnect lengths are decreased and signal propagation is faster, but manufacturing precision requirements increase

Engineering Contradiction:
Improvesignal propagation speedVSAvoidmanufacturing precision
Core Design Contradiction:
SpeedVSManufacturing precision

Solution Approach 1:

The patent incorporates test structures and test circuitry on each semiconductor die before the stacking process. These preliminary tests allow for verification of die functionality and identification of defects before bonding. Test structures include pad openings, test pads, and test circuitry that enable electrical testing of interconnects and circuit functionality at intermediate stages, ensuring quality control in the multi-die assembly process.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses substrate or carrier structures as intermediaries during the die stacking process. These substrates provide mechanical support, alignment features, and bonding surfaces that facilitate precise positioning and bonding of multiple dies. The substrate acts as a temporary carrier that holds dies in the correct spatial relationship during assembly, then can be removed after bonding is complete, enabling manufacturing precision in the stacked configuration.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Adaptability or versatility

If different types of devices are mixed and matched in a stack, then functionality and adaptability are enhanced, but ease of manufacture decreases

Engineering Contradiction:
ImprovefunctionalityVSAvoidease of manufacture
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent employs universal bonding interfaces and standardized test structures that can accommodate different types of semiconductor dies with various functionalities. The bonding pads, interconnect structures, and test circuitry are designed with universal characteristics that allow different die types (e.g., logic, memory, analog) to be stacked together using the same assembly process, enhancing adaptability while maintaining ease of manufacture through standardization.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables increased circuit density, reduced interconnect lengths, faster signal propagation, lower power dissipation, and the ability to mix different functionalities, resulting in more compact, efficient, and flexible electronic systems.

Implementation Method 1

The other die is disposed above the first die and is electrically coupled to the first die

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS9698123B2Apparatus for stacked electronic circuitry and associated methods
Publication Date: 2017.07.04 ALTERA CORP
  • US9698123B2 patent drawing
  • US9698123B2 patent drawing
  • US9698123B2 patent drawing

AI summary

An apparatus includes a substrate and a pair of die that include electronic circuitry. The substrate includes a cavity. One of the die is disposed in the cavity formed in the substrate. The other die is disposed above the first die and is electrically coupled to the first die.