3D IC Clock Distribution Using PLL Feedback Across Stacked Dies
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Solution Overview
Problem
Providing accurate clock signals in complex integrated circuit (IC) devices, particularly in three-dimensional (3D) IC devices with multiple stacked chips, is challenging due to time delays and jitter, which affect data accuracy and latency.
Innovation Solution
Implementing a phase-locked loop (PLL) in one semiconductor die to generate a clock signal for another die, with a feedback path to compensate for communication channel delays, and using multiplexers to select between master and local clock signals, ensuring robust data transmission and reduced latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock signals are transmitted between stacked semiconductor dies in 3D IC devices, then data transmission is enabled, but time delays and jitter occur affecting clock accuracy
Solution Approach 1:
The patent implements a feedback mechanism where the transmitted clock signal is returned from the second semiconductor die to the first die. This feedback path allows the system to measure and compensate for time delays and jitter that occur during clock signal transmission between dies, thereby maintaining clock accuracy despite the physical separation and communication channel delays.
Solution Approach 2:
The system performs preliminary calibration by transmitting test patterns and measuring actual time delays before normal operation. This preliminary measurement of communication channel delays enables the system to pre-compensate for timing issues, ensuring accurate clock synchronization is established before data transmission begins.
2Reliability
If FIFO circuits are used to handle timing variations, then data accuracy is maintained, but power consumption and area increase
Solution Approach 1:
The patent extracts and eliminates the need for FIFO (First-In-First-Out) buffering circuits by implementing a feedback-based clock synchronization mechanism. By returning the clock signal and compensating for delays actively, the system maintains data accuracy without requiring additional buffering infrastructure, thereby reducing both power consumption and chip area.
3Adaptability or versatility
If multiple clock domains are used in stacked dies, then functional independence is achieved, but clock synchronization becomes complex
Solution Approach 1:
The patent merges the clock domains by transmitting and returning clock signals between the first and second semiconductor dies. This allows both dies to operate with functionally independent logic while sharing a synchronized clock reference through the feedback mechanism, simplifying clock synchronization compared to completely independent clock domains.
Data Source
AI summary
An integrated circuit (IC) device includes first and second dies. The first die includes a first transmitting circuit, a first receiving circuit, and a first circuit. The first transmitting circuit transmits an output clock signal corresponding to a first clock signal. The first receiving circuit receives an input clock signal and an input signal, and outputs, based on the input clock signal, a first signal corresponding to the input signal. The first circuit outputs, based on the first clock signal, a second signal corresponding to the first signal. The second die includes a second receiving circuit coupled to the first transmitting circuit to receive the output clock signal, and a second transmitting circuit coupled to the first receiving circuit and transmitting to the first receiving circuit, based on the output clock signal, the input signal, and the input clock signal corresponding to the output clock signal.