Stacked Die Clock Repair for Inter-Die Timing Defects
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Solution Overview
Problem
Current testing schemes for 3D integrated circuits do not effectively account for defects in data transfer connections between dies, leading to timing delays and incorrect data transmission due to misalignment or suboptimal contact of micro-bumps, which can cause permanent or temporary failures.
Innovation Solution
A repair circuit is inserted in the clock line of downstream dies to compensate for delay defects by borrowing timing slack from intra-die paths, allowing the clock signal to be delayed by a predetermined amount to ensure correct data latching, thereby overcoming defects in inter-die connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Difficulty of detecting and measuring
If current testing schemes test one die at a time as stand-alone chips, then testing simplicity is maintained, but timing delays and defects in inter-die connections are not detected
Solution Approach 1:
The patent segments the testing process into multiple phases: initial stand-alone testing of each die, followed by stack assembly, and then inter-die connection testing. This segmentation allows simple individual die testing while enabling comprehensive defect detection when dies are stacked together, resolving the contradiction between testing simplicity and defect detection capability.
Solution Approach 2:
The patent introduces an intermediary testing mechanism that tests data transfer between dies through the inter-die connections (micro-bumps) without requiring complex external testing equipment. The dies themselves serve as the testing medium by transferring test data through the connection paths, enabling defect detection while maintaining relative testing simplicity.
2Manufacturing precision
If micro-bumps are used for data transfer between dies, then integration density is improved, but connection defects cause timing delays and data transmission errors
Solution Approach 1:
The patent performs preliminary testing of inter-die connections during the stack assembly process or before final packaging. By testing the micro-bump connections early, potential timing delays and defects are identified before the product reaches the customer, preventing reliability issues while maintaining the high integration density benefits of micro-bump technology.
Solution Approach 2:
The patent implements a feedback mechanism where test results from inter-die connection testing provide information about timing delays and defects. This feedback enables identification of problematic connections and allows for corrective actions or product sorting, thereby improving data transmission reliability while preserving the advantages of micro-bump based high-density integration.
3Reliability
If defect delay values are injected in inter-die connections, then timing budget is exceeded, but adding repair circuits increases device complexity
Solution Approach 1:
The patent applies partial compensation by adding delay circuits only to those specific inter-die connections that exhibit timing delays, rather than adding compensation to all connections. This selective approach maintains data latching accuracy for affected paths while minimizing the increase in overall device complexity.
Solution Approach 2:
The patent implements local quality by placing delay compensation circuits only at the specific locations where timing defects are detected in the inter-die connections. Rather than uniformly complicating the entire system, the repair circuits are localized to the problematic areas, thereby improving data latching accuracy where needed while keeping overall device complexity minimal.
Data Source
AI summary
Systems and methods are disclosed for testing a stack of dies and inserting a repair circuit which, when enabled, compensates for a delay defect in the die stack, particularly where the defect is located in the inter-die data transfer path. Intra-die and inter-die slack values are determined to establish which die or dies in the die stack would benefit from the insertion of a repair circuit.