Stacked Die Connectors for PoP Testing and CPI Protection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in achieving high integration density and component density in semiconductor devices while ensuring reliable testing and packaging of semiconductor dies, particularly in Package-on-Package (PoP) technology, where the need for smaller and more creative packaging techniques is essential.
Innovation Solution
The implementation of stacked vias and multiple passivation layers in semiconductor packages allows for effective testing and probing of chips while minimizing the risk of chip package interaction (CPI), ensuring that each chip is a known good die (KGD) and providing protection during and after testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If Package-on-Package technology is used to increase integration density, then component density is improved, but the risk of chip package interaction increases
Solution Approach 1:
The patent divides the package structure into distinct segments with separate encapsulants for each die, allowing independent testing and reducing interaction risks. The first die is encapsulated in a first encapsulant, and the second die is encapsulated in a second encapsulant, creating isolated testing environments that prevent chip package interaction while maintaining high component density through vertical stacking.
2Quantity of substance
If multiple dies are stacked to increase integration density, then device functionality is enhanced, but testing and probing becomes more difficult
Solution Approach 1:
The patent performs preliminary testing actions by exposing portions of the first die before final packaging. The first die is tested while exposed, allowing probing and measurement to be conducted before the die is encapsulated. This preliminary testing approach enables verification of die functionality at an earlier stage, making testing easier before the complexity of multi-die stacking increases.
3Manufacturing precision
If minimum feature size is reduced to increase integration density, then manufacturing precision is improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the manufacturing process into distinct stages for each die, with each die being processed, tested, and encapsulated separately. This segmentation allows standard manufacturing processes to be applied to each die independently, avoiding the need to simultaneously manage complex multi-die fabrication at reduced feature sizes, thereby maintaining manufacturing precision while reducing overall manufacturing complexity.
Data Source
AI summary
An embodiment is a method including forming a first die, the forming including forming through vias in a first substrate. The method also includes forming a first redistribution structure over the through vias and the first substrate, the first redistribution structure being electrically coupled to the through vias. The method also includes forming a first set of die connectors over and electrically coupled to the first redistribution structure, the first set of die connectors being on a first side of the first substrate. The method also includes bonding the first die to a second die. The method also includes encapsulating the first die with a first encapsulant. The method also includes forming a second set of die connectors over and electrically coupled to the first set of die connectors, the first and second sets of die connectors forming stacked die connectors.