Stacked Semiconductor Die Bonding With Cu Pads and Mold Protection

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Solution Overview

Problem

Existing semiconductor packages face challenges in reliability and durability due to issues such as non-bonding, voids, and cracks between stacked semiconductor dies, which affect the overall performance and longevity of the package.

Innovation Solution

A semiconductor package design featuring stacked semiconductor dies with specific conductive pad configurations and a robust bonding method using metal layers, including a Cu-to-Cu bonding process, to enhance adhesion and prevent surface deterioration during grinding processes, along with a mold layer to maintain die integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional bonding methods are used to stack semiconductor dies, then the manufacturing process is simple, but non-bonding, voids, and cracks occur between dies reducing reliability

Engineering Contradiction:

Improvebonding reliabilityVSAvoidbonding process complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent changes the bonding parameters by using Cu-to-Cu bonding with controlled bonding pressure and temperature, and by adjusting the metal layer thickness (50-200 nm) to achieve reliable bonding without voids and cracks

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent employs composite material structures with multiple metal layers (Cu, Ti, W) and diffusion barrier layers to create a robust bonding interface that prevents non-bonding and cracking while maintaining electrical conductivity

Inventive Principle:

Principle #40Composite materials

2Manufacturing precision

If grinding processes are applied to semiconductor dies, then the flatness is improved, but surface deterioration occurs

Engineering Contradiction:

Improvedie flatnessVSAvoidsurface deterioration

Core Design Contradiction:

Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The patent applies beforehand cushioning by forming a protective mold layer and optimizing the metal layer structure before the grinding process, which prevents surface deterioration while achieving the required flatness

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

The patent changes the material parameters by using specific metal combinations (Cu, Ti, W) with controlled thickness that maintain surface integrity during grinding while achieving precise flatness control

Inventive Principle:

Principle #35Parameter changes

3Reliability

If multiple metal layers and diffusion barrier layers are added to conductive pads, then adhesion and bonding reliability are enhanced, but the manufacturing process becomes more complex

Engineering Contradiction:

Improvebonding adhesionVSAvoidfabrication simplicity

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent applies segmentation by dividing the conductive pad structure into distinct functional layers (Cu layer for conductivity, Ti layer for adhesion, W layer for diffusion barrier), where each layer performs a specific function that collectively enhances bonding reliability

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by optimizing the thickness and material composition of each metal layer and diffusion barrier layer at specific locations to achieve maximum adhesion and bonding strength where needed

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design improves the topology and flatness of semiconductor dies, reducing process failures and increasing reliability by preventing non-bonding, void, and crack issues, thereby enhancing the overall performance and yield of the semiconductor package.

Implementation Method 1

performing a thermocompression process to bond the second metal layer, which is disposed on the device wafer, to the fourth metal layer, which is disposed on the carrier substrate

Methodology Applied

Scientific EffectThermocompression bonding:

Implementation Method 2

a back-side diffusion barrier layer covering the back-side conductive pad

Methodology Applied

Scientific EffectDiffusion barrier: Diffusion Barrier

Data Source

PatentUS20250379170A1Semiconductor package and method of fabricating the same

Publication Date: 2025.12.11 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor package includes: first to third semiconductor dies sequentially stacked on each other; and a mold layer covering the first to third semiconductor dies, wherein the second semiconductor die includes a first back-side conductive pad disposed in a top portion thereof, the third semiconductor die includes a first front-side conductive pad, which is disposed in a bottom portion thereof and is in contact with the first back-side conductive pad, each of the first front-side conductive pad and the first back-side conductive pad includes a first metal, and the first front-side conductive pad further includes a second metal that is different from the first metal.