Stacked Die Edge Metal Pads for Warpage and Thermal Resistance

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Solution Overview

Problem

Warpage of dies in 3D semiconductor packaging structures leads to bonding integrity issues and increased thermal resistance, disrupting heat conduction paths and affecting cooling efficiency.

Innovation Solution

Formation of peripheral metal pads at the corners or edges of dies using photolithography and electrochemical plating to reduce die warpage and enhance thermal conductivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If 3D packaging techniques are used to stack multiple IC devices vertically, then functional density and performance are improved, but die warpage occurs leading to bonding integrity issues and increased thermal resistance

Engineering Contradiction:
Improvefunctional densityVSAvoidbonding integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies local quality by forming metal pads specifically at the peripheral regions (corners or edges) of the dies rather than uniformly across the entire die surface. These localized metal pads provide targeted support to counteract warpage at critical bonding regions while maintaining the overall 3D stacking architecture. The metal pads are formed in recesses at specific locations to provide localized reinforcement where warpage most critically affects bonding integrity.

Inventive Principle:
Principle #3Local quality

2Productivity

If 3D packaging techniques are used to stack multiple IC devices vertically, then functional density is improved, but thermal resistance increases due to disrupted heat conduction paths

Engineering Contradiction:
Improvefunctional densityVSAvoidthermal resistance
Core Design Contradiction:
ProductivityVSTemperature

Solution Approach 1:

The patent addresses thermal resistance by forming metal pads at specific peripheral locations where they can serve as heat conduction pathways. These localized metal structures provide dedicated thermal conduction paths that bypass the die substrate, allowing heat to be efficiently conducted from the stacked dies to the heat sink. The metal pads are strategically positioned to optimize heat flow without disrupting the 3D stacking configuration.

Inventive Principle:
Principle #3Local quality

3Reliability

If peripheral metal pads are formed using photolithography and electrochemical plating, then die warpage is reduced and thermal conductivity is enhanced, but manufacturing process complexity increases

Engineering Contradiction:
Improvebonding integrityVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by forming the metal pads during the die fabrication process before the dies are stacked in the 3D packaging configuration. The metal pads are created in recesses on the die surface through photolithography and electrochemical plating, and then the dies are singulated and stacked. This sequencing allows the metal pads to be pre-formed and integrated into the die structure, avoiding the need for additional complex post-assembly steps to add thermal management features.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The peripheral metal pads act as electrically floating cushions, reducing die warpage and improving thermal performance by providing a high thermal conductivity heat conduction path, thereby enhancing bonding integrity and cooling efficiency.

Implementation Method 1

improving thermal performance by providing a high thermal conductivity heat conduction path

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

Formation of peripheral metal pads at the corners or edges of dies using photolithography and electrochemical plating

Methodology Applied
Scientific EffectElectrochemical plating: Electroplating

Data Source

PatentUS20250218987A1Thermal performance of stacked dies
Publication Date: 2025.07.03 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250218987A1 patent drawing
  • US20250218987A1 patent drawing
  • US20250218987A1 patent drawing

AI summary

A semiconductor package according to the present disclosure includes an interposer and a component mounted on the interposer. The component includes a first die and a second die disposed over the first die having a surface away from the first die. The second die includes a metal pad. A top surface of the metal pad is coplanar with the surface. The metal pad is electrically floating.