Stacked Die Edge Profile for Faster Wafer Singulation

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Solution Overview

Problem

The challenge in electronics manufacturing is the difficulty in singulating multiple IC dies, especially when they are stacked, due to the complexity of material layers and the thinness of IC wafers, which leads to slow and inefficient removal processes and potential dielectric cracking.

Innovation Solution

The proposed solution involves forming stacked die package structures with a specific edge region profile, comprising a curved first portion and a vertical second portion, which allows for increased singulation throughput using known chemistries and processes like laser scribe and saw/plasma etch processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple IC dies are stacked upon each other to increase integration, then the degree of integration is improved, but the wafer thickness is reduced making singulation increasingly difficult

Engineering Contradiction:
Improvedegree of integrationVSAvoidsingulation difficulty
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent applies preliminary action by forming a relief structure (removing material) from the backside of the wafer before the final singulation step. This pre-processing step creates a tapered edge profile that facilitates subsequent singulation by reducing the complexity of material removal and preventing dielectric cracking during the separation process.

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If various removal processes such as laser or chemical processes are used during singulation, then the ability to remove stack material is improved, but the process becomes slow and inefficient

Engineering Contradiction:
Improvematerial removal capabilityVSAvoidsingulation throughput
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The relief structure is formed in advance using material removal processes, preparing the wafer for faster subsequent singulation. By pre-removing material to create the tapered profile, the actual singulation step requires less material removal time, thereby increasing throughput while maintaining effective material removal capability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The singulation process is divided into two distinct stages: (1) forming the relief structure with tapered edges using material removal, and (2) performing the final separation cut. This segmentation allows each process to be optimized independently - the relief formation prepares the geometry for faster, cleaner separation in the second stage.

Inventive Principle:
Principle #1Segmentation

3Ease of manufacture

If conventional singulation processes are used on thin wafers with complex material layers, then the existing processes can be maintained, but dielectric cracking occurs reducing yield

Engineering Contradiction:
Improveprocess compatibilityVSAvoiddielectric integrity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The tapered edge profile is created as a preliminary step before final singulation. This pre-formed geometry reduces stress concentration at the edges during material removal and separation, preventing dielectric cracking while still using conventional laser or chemical processes that are compatible with existing manufacturing equipment.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables faster and more efficient wafer singulation, reducing the occurrence of dielectric cracking and improving overall yield, while maintaining the use of established processes.

Implementation Method 1

increased singulation throughput using known chemistries and processes like laser scribe

Methodology Applied
Scientific EffectLaser ablation: Laser Ablation

Implementation Method 2

laser scribe and saw/plasma etch processes

Methodology Applied
Scientific EffectPlasma etching: Plasma

Data Source

PatentUS12334472B2Multiple wafer stack architecture to enable singulation
Publication Date: 2025.06.17 INTEL CORP
  • US12334472B2 patent drawing
  • US12334472B2 patent drawing
  • US12334472B2 patent drawing

AI summary

Microelectronic stacked die package structures formed according to some embodiments may include a first die comprising a first conductive layer over a substrate layer. A second die may be on the first conductive layer. A third die is on the second die. An edge region of the stacked die package structure comprises a first portion over a second portion, the first portion comprising edges of the third die, the second die, and the first conductive layer, and the second portion comprising the substrate layer of the first die, wherein the first portion comprises a curved profile, and the second portion comprises a substantially vertical profile.