Stacked Die Package Structure With Encapsulation and Warpage Control
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Solution Overview
Problem
The semiconductor industry faces challenges in packaging System-on-Integrated-Chip (SoIC) components due to limitations in miniaturization, higher speed, bandwidth, and reduced power consumption, requiring innovative packaging techniques that enhance integration density and reduce latency.
Innovation Solution
A process flow involving chip-to-wafer fusion bonding, over-molding, grinding, and hybrid bonding techniques is employed to create a stacked structure of semiconductor dies with insulating encapsulation, redistribution layers, and conductive vias, allowing for precise alignment and bonding of multiple dies within a compact package, while using support substrates for warpage control and singulation to produce miniaturized SoIC components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If chip-to-wafer fusion bonding is used to stack multiple semiconductor dies, then integration density is improved, but manufacturing precision requirements increase
Solution Approach 1:
Alignment marks are formed on the semiconductor dies before bonding to guide precise positioning. The support substrate is prepared with specific mechanical properties in advance to control warpage during the bonding process, ensuring manufacturing precision is maintained while achieving high integration density through multi-die stacking.
2Volume of moving object
If multiple semiconductor dies are stacked to reduce package size, then volume is reduced, but device complexity increases
Solution Approach 1:
Multiple semiconductor dies are stacked vertically in a nested configuration, with each die placed on top of the previous one. This nesting approach reduces the horizontal package footprint while managing complexity through systematic layering and encapsulation of individual dies within the stacked structure.
Solution Approach 2:
The packaging process is divided into discrete steps including individual die bonding, encapsulation formation, and sequential die stacking. This segmentation allows each complex sub-process to be optimized independently, reducing overall packaging process complexity while achieving compact multi-die integration.
3Strength
If hybrid bonding techniques are employed for die stacking, then bonding strength is improved, but process complexity increases
Solution Approach 1:
Hybrid bonding combines different bonding mechanisms (e.g., direct bonding and eutectic bonding) to achieve superior bonding strength. The support substrate and encapsulation materials are selected as composite structures that facilitate both bonding modes, improving strength while managing process complexity through material selection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of compact, high-performance SoIC components with improved integration density, reduced latency, and enhanced bonding precision, addressing the need for smaller and more efficient packaging solutions.
Implementation Method 1
chip-to-wafer fusion bonding
Implementation Method 2
support substrates for warpage control
Data Source
AI summary
A structure including stacked substrates, a first semiconductor die, a second semiconductor die, and an insulating encapsulation is provided. The first semiconductor die is disposed over the stacked substrates. The second semiconductor die is stacked over the first semiconductor die. The insulating encapsulation includes a first encapsulation portion encapsulating the first semiconductor die and a second encapsulation portion encapsulating the second semiconductor die.